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authorvanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524>2008-03-14 05:58:31 +0000
committervanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524>2008-03-14 05:58:31 +0000
commit4beb4afe33ed6f3baaf126b146a1a9014d4d932f (patch)
tree27abe9d475643a98217dfaacb0bf175c4b5c521a
parentf0a83bb3087d050ed1eb33a36fb87dc32a488e83 (diff)
downloadedk2-platforms-4beb4afe33ed6f3baaf126b146a1a9014d4d932f.tar.xz
[Description]:
Fixed one bug in PciBus. PciBus doesn't clear the bridges bus number for all the root bridges before scanning any of them. [Impaction]: Pci Bus driver. [Reference Info]: EDK tracker 997. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@4851 6f19259b-4bc3-4df7-8a09-765794883524
-rw-r--r--IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c4
-rw-r--r--IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c73
2 files changed, 62 insertions, 15 deletions
diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
index edb12f6bb0..d64a6018e1 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
@@ -236,7 +236,9 @@ Returns:
RootBridgeHandle,
pConfiguration
);
-
+
+ gBS->FreePool (pConfiguration);
+
if (EFI_ERROR (Status)) {
return Status;
}
diff --git a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index d8cec4aaae..d35fe0d042 100644
--- a/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -4,14 +4,14 @@
It abstracts some functions that can be different
between light PCI bus driver and full PCI bus driver
-Copyright (c) 2006, Intel Corporation
-All rights reserved. This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2008, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -1297,7 +1297,7 @@ Returns:
//
// Add feature to support customized secondary bus number
//
- if (*SubBusNumber == 0) {
+ if (*SubBusNumber == 0) {
*SubBusNumber = *PaddedBusRange;
*PaddedBusRange = 0;
}
@@ -1481,7 +1481,7 @@ Returns:
}
DEBUG((EFI_D_ERROR, "Found DEV(%02d,%02d,%02d)\n", StartBusNumber, Device, Func ));
-
+
//
// Get the PCI device information
//
@@ -1594,7 +1594,7 @@ Returns:
//
// Add feature to support customized secondary bus number
//
- if (*SubBusNumber == 0) {
+ if (*SubBusNumber == 0) {
*SubBusNumber = *PaddedBusRange;
*PaddedBusRange = 0;
}
@@ -1860,9 +1860,15 @@ Returns:
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINT16 MinBus;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *pConfiguration;
+ UINT8 StartBusNumber;
+ LIST_ENTRY RootBridgeList;
+ LIST_ENTRY *Link;
InitializeHotPlugSupport ();
+ InitializeListHead (&RootBridgeList);
+
//
// Notify the bus allocation phase is about to start
//
@@ -1891,7 +1897,11 @@ Returns:
RootBridgeDev
);
- DestroyRootBridge (RootBridgeDev);
+ if (gPciHotPlugInit != NULL) {
+ InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));
+ } else {
+ DestroyRootBridge (RootBridgeDev);
+ }
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1906,8 +1916,43 @@ Returns:
if (gPciHotPlugInit != NULL) {
//
- // Wait for all HPC initialized
+ // Reset all assigned PCI bus number in all PPB
+ //
+ RootBridgeHandle = NULL;
+ Link = GetFirstNode (&RootBridgeList);
+ while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&
+ (!IsNull (&RootBridgeList, Link))) {
+ RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);
+ //
+ // Get the Bus information
+ //
+ Status = PciResAlloc->StartBusEnumeration (
+ PciResAlloc,
+ RootBridgeHandle,
+ (VOID **) &pConfiguration
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Get the bus number to start with
+ //
+ StartBusNumber = (UINT8) (pConfiguration->AddrRangeMin);
+
+ ResetAllPpbBusNumber (
+ RootBridgeDev,
+ StartBusNumber
+ );
+
+ gBS->FreePool (pConfiguration);
+ Link = GetNextNode (&RootBridgeList, Link);
+ DestroyRootBridge (RootBridgeDev);
+ }
+
//
+ // Wait for all HPC initialized
+ //
Status = AllRootHPCInitialized (STALL_1_SECOND * 15);
if (EFI_ERROR (Status)) {
@@ -1919,7 +1964,7 @@ Returns:
//
NotifyPhase (PciResAlloc, EfiPciHostBridgeBeginBusAllocation);
- DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));
+ DEBUG((EFI_D_ERROR, "PCI Bus Second Scanning\n"));
RootBridgeHandle = NULL;
while (PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) {