diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-06-02 11:13:21 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-06-07 09:56:59 +0800 |
| commit | 5397393f8e768359862b0e984bb2a35fdf580a95 (patch) | |
| tree | 1b84aa8e9f8d2722b1023f6ff2b2ddb28db87586 | |
| parent | 4eae41e03a636301c21b878f7b9f473c4d69d089 (diff) | |
| download | edk2-platforms-5397393f8e768359862b0e984bb2a35fdf580a95.tar.xz | |
BraswellPlatformPkg: Add PlatformPei.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/BootMode.c | 282 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/CommonHeader.h | 63 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/Generic/Recovery.c | 303 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/MemoryCallback.c | 219 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/Platform.c | 316 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/Platform.h | 165 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/PlatformPei.inf | 220 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/SetupVariableDefault.h | 1228 | ||||
| -rw-r--r-- | BraswellPlatformPkg/PlatformPei/Stall.c | 85 |
9 files changed, 2881 insertions, 0 deletions
diff --git a/BraswellPlatformPkg/PlatformPei/BootMode.c b/BraswellPlatformPkg/PlatformPei/BootMode.c new file mode 100644 index 0000000000..e90c95de78 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/BootMode.c @@ -0,0 +1,282 @@ +/** @file
+ EFI PEIM support boot paths to provide the platform.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "Platform.h"
+#include "PlatformBaseAddresses.h"
+#include "PchRegs.h"
+#include <Guid/SetupVariable.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/GpioLib.h>
+
+static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiMasterBootModePpiGuid,
+ NULL
+ },
+};
+
+
+EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiBootInRecoveryModePpiGuid,
+ NULL
+};
+
+BOOLEAN
+GetSleepTypeAfterWakeup (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT16 *SleepType
+ );
+
+UINT32
+GPIORead32 (
+ IN UINT32 mmio_conf
+ )
+{
+ UINT32 conf_val;
+ UINT32 i;
+ conf_val = MmioRead32(mmio_conf);
+ for(i=0;i<5;i++){
+ if(conf_val == 0xffffffff)
+ conf_val = MmioRead32(mmio_conf);
+ else
+ break;
+ }
+
+ return conf_val;
+}
+
+BOOLEAN
+CheckIfRecoveryMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+)
+{
+ PAD_VAL pad_val;
+
+ //
+ //
+ // Use GPIO_SUS0 as Recovery Jmper
+ // if short GPIO_SUS0 and Gnd then Recovery Jmper is setted
+ //
+ pad_val.dw = GPIORead32(IO_BASE_ADDRESS + GPIO_MMIO_OFFSET_N + 0x4800);
+ if (pad_val.r.pad_val == 0) {
+ DEBUG((EFI_D_INFO, "Recovery jumper setted!\n"));
+ return TRUE;
+ }
+ return FALSE;
+}
+
+/**
+ If the box was opened, it's boot with full config.
+ If the box is closed, then
+ 1. If it's first time to boot, it's boot with full config .
+ 2. If the ChassisIntrution is selected, force to be a boot with full config
+ 3. Otherwise it's boot with no change.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval TRUE If it's boot with no change.
+
+ @retval FALSE If boot with no change.
+**/
+BOOLEAN
+IsBootWithNoChange (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ BOOLEAN IsFirstBoot;
+ BOOLEAN EnableFastBoot;
+
+ IsFirstBoot = PcdGetBool(PcdBootState);
+ EnableFastBoot = PcdGetBool (PcdEnableFastBoot);
+
+ DEBUG ((EFI_D_INFO, "IsFirstBoot = %x , EnableFastBoot= %x. \n", IsFirstBoot, EnableFastBoot));
+
+ if ((!IsFirstBoot) && EnableFastBoot) {
+ PcdSetBool (PcdBootToFirmwareUserInterface, FALSE);
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+
+EFI_STATUS
+UpdateBootMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT16 SleepType;
+#ifdef EFI_DEBUG
+ CHAR16 *strBootMode;
+#endif
+
+ Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+
+ ASSERT_EFI_ERROR (Status);
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ return Status;
+ }
+
+ //
+ // Let's assume things are OK if not told otherwise
+ //
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+ if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+
+ case V_PCH_ACPI_PM1_CNT_S4:
+// BootMode = BOOT_ON_S4_RESUME;
+ break;
+
+ case V_PCH_ACPI_PM1_CNT_S5:
+// BootMode = BOOT_ON_S5_RESUME;
+ break;
+ } // switch (SleepType)
+ }
+
+
+ //
+ // Check if we need to boot in forced recovery mode
+ //
+ if (CheckIfRecoveryMode(PeiServices)) {
+ DEBUG ((EFI_D_INFO, "Boot mode on recovery mode\n"));
+ Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
+ BootMode = BOOT_IN_RECOVERY_MODE;
+ } else if (IsBootWithNoChange(PeiServices)) {
+ if(BootMode != BOOT_ON_S3_RESUME) {
+ BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
+ }
+ }
+
+#ifdef EFI_DEBUG
+ switch (BootMode) {
+ case BOOT_WITH_FULL_CONFIGURATION:
+ strBootMode = L"BOOT_WITH_FULL_CONFIGURATION";
+ break;
+ case BOOT_WITH_MINIMAL_CONFIGURATION:
+ strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION";
+ break;
+ case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
+ strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";
+ break;
+ case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
+ strBootMode = L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";
+ break;
+ case BOOT_WITH_DEFAULT_SETTINGS:
+ strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS";
+ break;
+ case BOOT_ON_S4_RESUME:
+ strBootMode = L"BOOT_ON_S4_RESUME";
+ break;
+ case BOOT_ON_S5_RESUME:
+ strBootMode = L"BOOT_ON_S5_RESUME";
+ break;
+ case BOOT_ON_S2_RESUME:
+ strBootMode = L"BOOT_ON_S2_RESUME";
+ break;
+ case BOOT_ON_S3_RESUME:
+ strBootMode = L"BOOT_ON_S3_RESUME";
+ break;
+ case BOOT_ON_FLASH_UPDATE:
+ strBootMode = L"BOOT_ON_FLASH_UPDATE";
+ break;
+ case BOOT_IN_RECOVERY_MODE:
+ strBootMode = L"BOOT_IN_RECOVERY_MODE";
+ break;
+ default:
+ strBootMode = L"Unknown boot mode";
+ } // switch (BootMode)
+
+ DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode));
+#endif
+ Status = (*PeiServices)->SetBootMode (PeiServices, BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Get sleep type after wakeup
+
+ @param[in] PeiServices Pointer to the PEI Service Table.
+ @param[out] SleepType Sleep type to be returned.
+
+ @retval TRUE A wake event occured without power failure.
+ @retval FALSE Power failure occured or not a wakeup.
+
+**/
+BOOLEAN
+GetSleepTypeAfterWakeup (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT16 *SleepType
+ )
+{
+ UINT16 Pm1Sts;
+ UINT16 Pm1Cnt;
+ UINT16 GenPmCon1;
+
+ //
+ // VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure Consideration"
+ //
+ // When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost.
+ // This bit is in the SUS Well and defaults to 1’b1 based on RSMRST# assertion (not cleared by any type of reset).
+ // System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE + 0x20[14]),
+ // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1’b1
+ // regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field.
+ //
+ GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);
+ //
+ // Read the ACPI registers
+ //
+ Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
+ Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);
+
+ if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||
+ (Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {
+ // If power failure indicator, then don't attempt s3 resume.
+ // Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has
+ // lost already. This is to make sure no one will use PM1_CNT to check for S3 after
+ // power failure.
+ if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
+ Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5);
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+ }
+ }
+ //
+ // Get sleep type if a wake event occurred and there is no power failure
+ //
+ if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
+ *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
+ return TRUE;
+ } else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4) {
+ *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
diff --git a/BraswellPlatformPkg/PlatformPei/CommonHeader.h b/BraswellPlatformPkg/PlatformPei/CommonHeader.h new file mode 100644 index 0000000000..23b2ac4715 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/CommonHeader.h @@ -0,0 +1,63 @@ +/** @file
+ Common header file shared by all source files.
+ This file includes package header files, library classes and protocol, PPI & GUID definitions.
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __COMMON_HEADER_H_
+#define __COMMON_HEADER_H_
+
+#include <FrameworkPei.h>
+#include <IndustryStandard/SmBus.h>
+#include <IndustryStandard/Pci22.h>
+#include <Ppi/AtaController.h>
+#include <Guid/Capsule.h>
+#include <Ppi/Cache.h>
+#include <Ppi/MasterBootMode.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/RecoveryDevice.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/FvLoadFile.h>
+#include <Ppi/DeviceRecoveryModule.h>
+#include <Ppi/Capsule.h>
+#include <Ppi/Reset.h>
+#include <Ppi/Stall.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/Smbus2.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/DebugLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/PciCf8Lib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ResetSystemLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/RecoveryOemHookLib.h>
+
+#endif
diff --git a/BraswellPlatformPkg/PlatformPei/Generic/Recovery.c b/BraswellPlatformPkg/PlatformPei/Generic/Recovery.c new file mode 100644 index 0000000000..4813a77587 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/Generic/Recovery.c @@ -0,0 +1,303 @@ +/** @file
+ This file provides the implementatin of EFI_PEI_DEVICE_RECOVERY_MODULE_PPI,
+ it does following
+ 1. Determine the number of DXE recovery capsules found by each device
+ 2. Determine capsule information
+ 3. Load a specific DXE recovery capsule from the indicated device
+ 4. Determine the device load order
+ The capsule is security verified and decomposed and the HOB table is updated
+ with the DXE recovery firmware volume.
+
+ The recovery capsule is determined by 2 factors,
+ 1. The device search order, if more than one Device Recovery Module PPI
+ was discovered
+ 2. The individual search order, if the device reported more than one recovery
+ DXE capsule was found generating a search order list.
+
+ The 2 orders are decided by the RecoveryOemHook library function OemRecoveryRankCapsule().
+
+ The security check and error handling is done by RecoveryOemHook library function
+ OemRecoverySecurityCheck()
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "CommonHeader.h"
+
+EFI_STATUS
+EFIAPI
+PlatformRecoveryModule (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This
+ );
+
+STATIC EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = {
+ PlatformRecoveryModule
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiRecoveryModulePpiGuid,
+ &mRecoveryPpi
+ }
+};
+
+/**
+ This function initialize recovery functionality by installing the recovery PPI.
+
+ @param PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS if the interface could be successfully installed.
+**/
+EFI_STATUS
+EFIAPI
+InitializeRecovery (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesInstallPpi (mRecoveryPpiList);
+
+ return Status;
+}
+
+/**
+ Loads a DXE capsule from some media into memory and updates the HOB table
+ with the DXE firmware volume information.
+
+ @param PeiServices General-purpose services that are available to every PEIM.
+ @param This Indicates the EFI_PEI_RECOVERY_MODULE_PPI instance.
+
+ @retval EFI_SUCCESS The capsule was loaded correctly.
+ @retval EFI_DEVICE_ERROR A device error occurred.
+ @retval EFI_NOT_FOUND A recovery DXE capsule cannot be found.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformRecoveryModule (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule;
+ UINTN RecoveryCapsuleSize;
+ EFI_GUID DeviceId;
+ EFI_PHYSICAL_ADDRESS Address;
+ VOID *Buffer;
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_PEI_HOB_POINTERS HobOld;
+ BOOLEAN HobUpdate;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ UINTN DeviceInstance;
+ UINTN CapsuleInstance;
+
+ DeviceInstance = 0;
+ CapsuleInstance = 1;
+ RecoveryCapsuleSize = 0;
+ Status = EFI_NOT_FOUND;
+ HobUpdate = FALSE;
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Entry\n"));
+
+ //
+ // Search the platform for some recovery capsule if the DXE IPL
+ // discovered a recovery condition and has requested a load.
+ //
+ while (OemRecoveryRankCapsule(
+ &DeviceInstance,
+ &CapsuleInstance,
+ &DeviceRecoveryModule,
+ &Buffer
+ )) {
+
+ DEBUG ((
+ EFI_D_INFO | EFI_D_LOAD,
+ "Recovery Capsule ranked DeviceInstance = %x CapsuleInstance = %x\n",
+ DeviceInstance,
+ CapsuleInstance
+ ));
+
+ if (Buffer == NULL) {
+
+ //
+ // The OemRecoveryRankCapsule() does not reurn a capsule, load it by CapsuleInstance.
+ //
+
+ if (DeviceRecoveryModule == NULL) {
+
+ //
+ // The OemRecoveryRankCapsule() does not reurn a devide PPI, load it by DeviceInstance.
+ //
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiDeviceRecoveryModulePpiGuid,
+ DeviceInstance,
+ NULL,
+ (VOID **) &DeviceRecoveryModule
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Randked Device Recovery PPI not located\n"));
+ DeviceInstance ++;
+ continue;
+ }
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n"));
+ }
+
+ Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (
+ PeiServices,
+ DeviceRecoveryModule,
+ CapsuleInstance,
+ &RecoveryCapsuleSize,
+ &DeviceId
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Unknown Recovery Capsule Size\n"));
+ CapsuleInstance ++;
+ continue;
+ }
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize));
+
+ DEBUG((EFI_D_INFO,
+ "PcdRecoveryOnIdeDisk = %x \n",
+ FeaturePcdGet (PcdRecoveryOnIdeDisk)
+ ));
+ DEBUG((EFI_D_INFO,
+ "PcdRecoveryOnFatFloppyDisk = %x \n",
+ FeaturePcdGet (PcdRecoveryOnFatFloppyDisk)
+ ));
+ DEBUG((EFI_D_INFO,
+ "PcdRecoveryOnDataCD = %x \n",
+ FeaturePcdGet (PcdRecoveryOnDataCD)
+ ));
+ DEBUG((EFI_D_INFO,
+ "PcdRecoveryOnFatUsbDisk = %x \n",
+ FeaturePcdGet (PcdRecoveryOnFatUsbDisk)
+ ));
+ //
+ // Detect whether it's a supported media
+ //
+ if ((!FeaturePcdGet (PcdRecoveryOnIdeDisk) ||
+ !CompareGuid (&DeviceId, &gRecoveryOnFatIdeDiskGuid)) &&
+ (!FeaturePcdGet (PcdRecoveryOnFatFloppyDisk) ||
+ !CompareGuid (&DeviceId, &gRecoveryOnFatFloppyDiskGuid)) &&
+ (!FeaturePcdGet (PcdRecoveryOnDataCD) ||
+ !CompareGuid (&DeviceId, &gRecoveryOnDataCdGuid)) &&
+ (!FeaturePcdGet (PcdRecoveryOnFatUsbDisk) ||
+ !CompareGuid (&DeviceId, &gRecoveryOnFatUsbDiskGuid))
+ ) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery media not supported\n"));
+ CapsuleInstance ++;
+ continue;
+ }
+
+ Buffer = NULL;
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "AllocatePage Pagess: %x\n", EFI_SIZE_TO_PAGES (RecoveryCapsuleSize)));
+
+ Status = PeiServicesAllocatePages (
+ EfiBootServicesCode,
+ EFI_SIZE_TO_PAGES (RecoveryCapsuleSize),
+ &Address
+ );
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "AllocatePage Returns: %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ CapsuleInstance ++;
+ continue;
+ }
+
+
+ Buffer = (UINT8*)(UINTN)Address;
+ Status = DeviceRecoveryModule->LoadRecoveryCapsule (
+ PeiServices,
+ DeviceRecoveryModule,
+ CapsuleInstance,
+ Buffer
+ );
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status));
+ if (EFI_ERROR (Status)) {
+ CapsuleInstance ++;
+ continue;
+ }
+ } // end of (Buffer == NULL)
+
+ if (!OemRecoverySecurityCheck (Buffer)) {
+ CapsuleInstance ++;
+ continue;
+ }
+
+ //
+ // Update FV Hob if found
+ //
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ HobOld.Raw = Hob.Raw;
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_FV) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length));
+
+ if (Hob.FirmwareVolume->BaseAddress == (UINTN) PcdGet32 (PcdFlashFvMainBase)) {
+ HobUpdate = TRUE;
+ //
+ // This looks like the Hob we are interested in
+ //
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n"));
+ Hob.FirmwareVolume->BaseAddress = (UINTN)Buffer;
+ Hob.FirmwareVolume->Length = RecoveryCapsuleSize;
+
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ //
+ // Check if the top of the file is a firmware volume header
+ //
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Buffer;
+ if (FvHeader->Signature== EFI_FVH_SIGNATURE) {
+ //
+ // build FV Hob if it is not built before
+ //
+ if (!HobUpdate) {
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n" ));
+
+ BuildFvHob (
+ (EFI_PHYSICAL_ADDRESS) (UINTN) Buffer,
+ (UINT32) FvHeader->FvLength
+ );
+ }
+
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ Buffer,
+ (UINT32) FvHeader->FvLength,
+ NULL,
+ NULL
+ );
+ }
+
+ //
+ // Capsule is loaded and HOB list is updated, done.
+ //
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule is loaded: %r\n", Status));
+
+ break;
+ } // end of while
+
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n", Status));
+ return Status;
+}
+
+
+
diff --git a/BraswellPlatformPkg/PlatformPei/MemoryCallback.c b/BraswellPlatformPkg/PlatformPei/MemoryCallback.c new file mode 100644 index 0000000000..c212383a34 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/MemoryCallback.c @@ -0,0 +1,219 @@ +/** @file
+ This file includes a memory call back function notified when MRC is done,
+ following action is performed in this file,
+ 1. ICH initialization after MRC.
+ 2. SIO initialization.
+ 3. Install ResetSystem and FinvFv PPI.
+ 4. Set MTRR for PEI
+ 5. Create FV HOB and Flash HOB
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "Platform.h"
+#include <Ppi/Cache.h>
+#include <Library/BaseCryptLib.h>
+#include <Guid/PlatformInfo.h>
+#include "ChvAccess.h"
+
+/**
+ This function will be called when MRC is done.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Information about the notify event..
+ @param[in] Ppi The notify context.
+
+ @retval EFI_SUCCESS If the function completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT32 Pages;
+ VOID* Memory;
+ UINTN Size;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ UINT32 FvAlignment;
+
+ Status = (*PeiServices)->GetBootMode (
+ (const EFI_PEI_SERVICES **)PeiServices,
+ &BootMode
+ );
+
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ //
+ // Install Recovery PPI
+ //
+ Status = InitializeRecovery ((EFI_PEI_SERVICES **)PeiServices);
+ ASSERT_EFI_ERROR (Status);
+
+ }
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ Size = PcdGet32(PcdFlashFvRecovery2Size);
+ if (Size > 0) {
+ Pages= (Size + 0xFFF)/0x1000;
+
+ Memory = AllocatePages ( Pages );
+ CopyMem(Memory , (VOID *) PcdGet32(PcdFlashFvRecovery2Base) , Size);
+
+ //
+ // We don't verify just load
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) Memory,
+ PcdGet32 (PcdFlashFvRecovery2Size),
+ NULL,
+ NULL
+ );
+ }
+
+ if (BootMode != BOOT_IN_RECOVERY_MODE){
+ Size = PcdGet32(PcdFlashFvMainSize);
+ Pages= (Size + 0xFFF)/0x1000;
+
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32(PcdFlashFvMainBase);
+
+ //
+ // Check the FV alignment
+ //
+ if ((FvHeader->Attributes & EFI_FVB2_WEAK_ALIGNMENT) != EFI_FVB2_WEAK_ALIGNMENT) {
+ //
+ // Get FvHeader alignment
+ //
+ FvAlignment = 1 << ((FvHeader->Attributes & EFI_FVB2_ALIGNMENT) >> 16);
+ //
+ // FvAlignment must be greater than or equal to 8 bytes of the minimum FFS alignment value.
+ //
+ if (FvAlignment < 8) {
+ FvAlignment = 8;
+ }
+ Memory = AllocateAlignedPages (Pages, FvAlignment);
+ } else {
+ Memory = AllocatePages ( Pages );
+ }
+ CopyMem(Memory , (VOID *) PcdGet32(PcdFlashFvMainBase) , Size);
+
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) Memory,
+ PcdGet32 (PcdFlashFvMainSize),
+ NULL,
+ NULL
+ );
+ }
+ }
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) (UINTN) (PcdGet32 (PcdFlashFvRecovery2Base)),
+ PcdGet32 (PcdFlashFvRecovery2Size),
+ NULL,
+ NULL
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EndOfPeiPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_FV_INFO VolumeInfo;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_FV_FILE_INFO FileInfo;
+ UINTN FfsCount;
+ UINTN FvImageCount;
+ Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Check whether FVMAIN is compressed. If not, we will publish fv hob here in Normal Boot..
+ //
+ //
+ // Determine if Main FV is only composed of FV Image files
+ //
+ if (BootMode != BOOT_ON_S3_RESUME && BootMode != BOOT_IN_RECOVERY_MODE) {
+ Instance = 0;
+ while (TRUE) {
+ //
+ // Traverse all firmware volume instances to find FV Main instance
+ //
+ Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ Status = PeiServicesFfsGetVolumeInfo(VolumeHandle, &VolumeInfo);
+ if (EFI_ERROR (Status)) {
+ Instance++;
+ continue;
+ }
+
+ if (VolumeInfo.FvSize != PcdGet32 (PcdFlashFvMainSize)) {
+ Instance++;
+ continue;
+ }
+
+ //
+ // Count total number of FFS files and number of FV Image files in FV Main.
+ //
+ FileHandle = NULL;
+ FfsCount = 0;
+ FvImageCount = 0;
+ while (TRUE) {
+ Status = PeiServicesFfsFindNextFile (EFI_FV_FILETYPE_ALL, VolumeHandle, &FileHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ FfsCount++;
+ Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ if (FileInfo.FileType == EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE) {
+ FvImageCount++;
+ }
+ }
+ //
+ // If number if FFS files is not the same as the number of FV Image files,
+ // then publish HOB for FV Main so it is available for use in the DXE Phase.
+ //
+ if (FfsCount != FvImageCount) {
+ BuildFvHob (
+ (UINTN)VolumeInfo.FvStart,
+ VolumeInfo.FvSize
+ );
+ DEBUG ((EFI_D_INFO, "FVMAIN Fv Hob Built, BaseAddress=0x%x, Size=%x\n", VolumeInfo.FvStart, VolumeInfo.FvSize));
+ }
+ break;
+ }
+ }
+
+ return Status;
+}
diff --git a/BraswellPlatformPkg/PlatformPei/Platform.c b/BraswellPlatformPkg/PlatformPei/Platform.c new file mode 100644 index 0000000000..bd8cb33e67 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/Platform.c @@ -0,0 +1,316 @@ +/** @file
+ This PEIM initialize platform for MRC, following action is performed,
+ 1. Initialize GMCH
+ 2. Detect boot mode
+ 3. Detect video adapter to determine whether we need pre-allocated memory
+ 4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.
+ This file contains the main entry point of the PEIM.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "Platform.h"
+#include "PlatformBaseAddresses.h"
+#include "PchRegs.h"
+#include <Guid/PlatformInfo.h>
+#include "ChvAccess.h"
+#include <Library/GpioLib.h>
+#include <Guid/Chv2Variable.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Ppi/BoardDetection.h>
+#include <Guid/SetupVariable.h>
+#include "SetupVariableDefault.h"
+
+#ifndef EC_BASE
+#define EC_BASE ((UINTN)PcdGet64(PcdPciExpressBaseAddress))
+#endif
+
+#ifndef MmPciAddress
+#define MmPciAddress(Segment, Bus, Device, Function, Register) \
+ ((UINTN) EC_BASE + \
+ (UINTN) (Bus << 20) + \
+ (UINTN) (Device << 15) + \
+ (UINTN) (Function << 12) + \
+ (UINTN) (Register) \
+ )
+#endif
+
+//
+// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory
+//
+
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ );
+
+static EFI_PEI_STALL_PPI mStallPpi = {
+ PEI_STALL_RESOLUTION,
+ Stall
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiStallPpiGuid,
+ &mStallPpi
+ }
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ MemoryDiscoveredPpiNotifyCallback
+ }
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiEndOfPeiSignalPpiGuid,
+ EndOfPeiPpiNotifyCallback
+ }
+};
+static EFI_PEI_PPI_DESCRIPTOR mBoardDetectionStartPpi[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBoardDetectionStartPpiGuid,
+ NULL
+ }
+};
+STATIC
+EFI_STATUS
+CheckSetupVarItem (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ DEBUG ((EFI_D_INFO, "CheckSetupVarItem(): entry \n"));
+ if (SystemConfiguration->TurboModeEnable > 1)
+ SystemConfiguration->TurboModeEnable = PcdGet8(PcdTurboMode);
+ //
+ // South Complex
+ //
+ if (SystemConfiguration->SccSdcardEnabled > 2)
+ SystemConfiguration->SccSdcardEnabled = PcdGet8(PcdSdcardMode);
+ if (SystemConfiguration->LpssHsuart0Enabled > 2)
+ SystemConfiguration->LpssHsuart0Enabled = PcdGet8(PcdEnableHsuart0);
+ if (SystemConfiguration->LpssHsuart1Enabled > 2)
+ SystemConfiguration->LpssHsuart1Enabled = PcdGet8(PcdEnableHsuart1);
+ if (SystemConfiguration->PchAzalia > 1)
+ SystemConfiguration->PchAzalia = PcdGet8(PcdEnableAzalia);
+ if (SystemConfiguration->PchSata > 1)
+ SystemConfiguration->PchSata = PcdGet8(PcdEnableSata);
+ if (SystemConfiguration->PchUsb30Mode > 1)
+ SystemConfiguration->PchUsb30Mode = PcdGet8(PcdEnableXhci);
+ if (SystemConfiguration->PchLpeEnabled > 2)
+ SystemConfiguration->PchLpeEnabled = PcdGet8(PcdEnableLpe);
+ if (SystemConfiguration->LpssDma0Enabled > 2)
+ SystemConfiguration->LpssDma0Enabled = PcdGet8(PcdEnableDma0);
+ if (SystemConfiguration->LpssDma1Enabled > 2)
+ SystemConfiguration->LpssDma1Enabled = PcdGet8(PcdEnableDma1);
+ if (SystemConfiguration->LpssI2C0Enabled > 2)
+ SystemConfiguration->LpssI2C0Enabled = PcdGet8(PcdEnableI2C0);
+ if (SystemConfiguration->LpssI2C1Enabled > 2)
+ SystemConfiguration->LpssI2C1Enabled = PcdGet8(PcdEnableI2C1);
+ if (SystemConfiguration->LpssI2C2Enabled > 2)
+ SystemConfiguration->LpssI2C2Enabled = PcdGet8(PcdEnableI2C2);
+ if (SystemConfiguration->LpssI2C3Enabled > 2)
+ SystemConfiguration->LpssI2C3Enabled = PcdGet8(PcdEnableI2C3);
+ if (SystemConfiguration->LpssI2C4Enabled > 2)
+ SystemConfiguration->LpssI2C4Enabled = PcdGet8(PcdEnableI2C4);
+ if (SystemConfiguration->LpssI2C5Enabled > 2)
+ SystemConfiguration->LpssI2C5Enabled = PcdGet8(PcdEnableI2C5);
+ if (SystemConfiguration->LpssI2C6Enabled > 2)
+ SystemConfiguration->LpssI2C6Enabled = PcdGet8(PcdEnableI2C6);
+ if (SystemConfiguration->ScceMMCEnabled > 2)
+ SystemConfiguration->ScceMMCEnabled = PcdGet8(PcdEmmcMode);
+ if (SystemConfiguration->SataInterfaceSpeed > 3)
+ SystemConfiguration->SataInterfaceSpeed = PcdGet8(PcdSataInterfaceSpeed);
+ if (SystemConfiguration->ISPEn > 1)
+ SystemConfiguration->ISPEn = PcdGet8(ISPEnable);
+ if (SystemConfiguration->ISPDevSel > 2)
+ SystemConfiguration->ISPDevSel = PcdGet8(ISPPciDevConfig);
+ if (SystemConfiguration->MrcDvfsEnable > 1)
+ SystemConfiguration->MrcDvfsEnable = PcdGet8(PcdDvfsEnable);
+ if (SystemConfiguration->PnpSettings > 5)
+ SystemConfiguration->PnpSettings = PcdGet8(PcdPnpSettings);
+
+ //
+ // North Complex
+ //
+ if (SystemConfiguration->GTTSize > 2)
+ SystemConfiguration->GTTSize = PcdGet8(PcdGttSize);
+
+ if (SystemConfiguration->IgdApertureSize > 3)
+ SystemConfiguration->IgdApertureSize = PcdGet8(PcdApertureSize);
+
+ if (SystemConfiguration->IgdDvmt50PreAlloc > 16)
+ SystemConfiguration->IgdDvmt50PreAlloc = PcdGet8(PcdIgdDvmt50PreAlloc);
+
+
+ DEBUG ((EFI_D_INFO, "CheckSetupVarItem(): exit \n"));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetSetupVariable (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ UINTN VariableSize;
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
+
+ Status = (*PeiServices)->LocatePpi (PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ &Variable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Use normal setup default from NVRAM variable,
+ // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
+ //
+ VariableSize = sizeof(SYSTEM_CONFIGURATION);
+ Status = Variable->GetVariable (Variable,
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ SystemConfiguration);
+ if (VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
+ DEBUG ((EFI_D_ERROR, "Setup variable is currputed\n"));
+ Status = EFI_BAD_BUFFER_SIZE;
+ }
+ DEBUG ((EFI_D_INFO, "GetSetupVariable() Exit \n"));
+ return Status;
+}
+
+/**
+ This is the entry point of PEIM
+
+ @param[in] FileHandle Handle of the file being invoked.
+ @param[in] PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS If it is completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiInitPlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN Size;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ //
+ // Get setup variable. This can only be done after BootMode is updated
+ //
+ Status = GetSetupVariable (PeiServices, &SystemConfiguration);
+ Size = sizeof(SYSTEM_CONFIGURATION);
+
+ if(EFI_ERROR(Status)){
+ //
+ // For OC solution, there is no setup variable, so set the SystemConfiguration with default value.
+ //
+ CopyMem(&SystemConfiguration, &gDefaultSystemConfiguration,Size);
+ //
+ // Update the values according to PCD settings
+ //
+
+ //
+ // Platform
+ //
+ SystemConfiguration.TurboModeEnable = PcdGet8(PcdTurboMode);
+
+ //
+ // South Complex
+ //
+ SystemConfiguration.SccSdcardEnabled = PcdGet8(PcdSdcardMode);
+ SystemConfiguration.LpssHsuart0Enabled = PcdGet8(PcdEnableHsuart0);
+ SystemConfiguration.LpssHsuart1Enabled = PcdGet8(PcdEnableHsuart1);
+ SystemConfiguration.PchAzalia = PcdGet8(PcdEnableAzalia);
+ SystemConfiguration.PchSata = PcdGet8(PcdEnableSata);
+ SystemConfiguration.PchUsb30Mode = PcdGet8(PcdEnableXhci);
+ SystemConfiguration.PchLpeEnabled = PcdGet8(PcdEnableLpe);
+ SystemConfiguration.LpssDma0Enabled = PcdGet8(PcdEnableDma0);
+ SystemConfiguration.LpssDma1Enabled = PcdGet8(PcdEnableDma1);
+ SystemConfiguration.LpssI2C0Enabled = PcdGet8(PcdEnableI2C0);
+ SystemConfiguration.LpssI2C1Enabled = PcdGet8(PcdEnableI2C1);
+ SystemConfiguration.LpssI2C2Enabled = PcdGet8(PcdEnableI2C2);
+ SystemConfiguration.LpssI2C3Enabled = PcdGet8(PcdEnableI2C3);
+ SystemConfiguration.LpssI2C4Enabled = PcdGet8(PcdEnableI2C4);
+ SystemConfiguration.LpssI2C5Enabled = PcdGet8(PcdEnableI2C5);
+ SystemConfiguration.LpssI2C6Enabled = PcdGet8(PcdEnableI2C6);
+ SystemConfiguration.ScceMMCEnabled = PcdGet8(PcdEmmcMode);
+ SystemConfiguration.SataInterfaceSpeed = PcdGet8(PcdSataInterfaceSpeed);
+ SystemConfiguration.ISPEn = PcdGet8(ISPEnable);
+ SystemConfiguration.ISPDevSel = PcdGet8(ISPPciDevConfig);
+ SystemConfiguration.PchSata = PcdGet8(PcdEnableSata);
+ SystemConfiguration.MrcDvfsEnable = PcdGet8(PcdDvfsEnable);
+ SystemConfiguration.PnpSettings = PcdGet8(PcdPnpSettings);
+
+ //
+ // North Complex
+ //
+ SystemConfiguration.GTTSize = PcdGet8(PcdGttSize);
+ SystemConfiguration.IgdApertureSize = PcdGet8(PcdApertureSize);
+ SystemConfiguration.IgdDvmt50PreAlloc = PcdGet8(PcdIgdDvmt50PreAlloc);
+ SystemConfiguration.TSEGSizeSel = (UINT8)PcdGet16(PcdMrcInitTsegSize);
+ DEBUG ((EFI_D_INFO, "PeiInitPlatform(): GetSetupVariable returns EFI_NOT_FOUND!! \n"));
+ }else {
+ // Chipsec: Go thrugh all setup items is corrupted one by one
+ CheckSetupVarItem(&SystemConfiguration);
+ }
+ PcdSetPtr (PcdSystemConfiguration, &Size, &SystemConfiguration);
+ DEBUG ((EFI_D_INFO, "PcdSystemConfiguration size - 0x%x\n", LibPcdGetExSize(&gEfiEdkIIPlatformTokenSpaceGuid, PcdTokenEx(&gEfiEdkIIPlatformTokenSpaceGuid, PcdSystemConfiguration)) ));
+
+ //
+ // Initialize Stall PPIs
+ //
+ Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = (*PeiServices)->NotifyPpi (PeiServices, &mMemoryDiscoveredNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+ Status = (*PeiServices)->NotifyPpi (PeiServices, &mEndOfPeiNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Start board detection
+ //
+ Status = PeiServicesInstallPpi (mBoardDetectionStartPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set the new boot mode for MRC
+ //
+ Status = UpdateBootMode (PeiServices);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/BraswellPlatformPkg/PlatformPei/Platform.h b/BraswellPlatformPkg/PlatformPei/Platform.h new file mode 100644 index 0000000000..af6a2eb8f9 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/Platform.h @@ -0,0 +1,165 @@ +/** @file
+ The header file of Platform PEIM.
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PEI_PLATFORM_H__
+#define __PEI_PLATFORM_H__
+
+#define PEI_STALL_RESOLUTION 1
+#define STALL_PEIM_SIGNATURE SIGNATURE_32('p','p','u','s')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_FFS_FILE_HEADER *FfsHeader;
+ EFI_PEI_NOTIFY_DESCRIPTOR StallNotify;
+} STALL_CALLBACK_STATE_INFORMATION;
+
+#define STALL_PEIM_FROM_THIS(a) CR (a, STALL_CALLBACK_STATE_INFORMATION, StallNotify, STALL_PEIM_SIGNATURE)
+
+/**
+ Peform the boot mode determination logic
+ If the box is closed, then
+ 1. If it's first time to boot, it's boot with full config .
+ 2. If the ChassisIntrution is selected, force to be a boot with full config
+ 3. Otherwise it's boot with no change.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS If the boot mode could be set
+
+**/
+EFI_STATUS
+UpdateBootMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ This function reset the entire platform, including all processor and devices, and
+ reboots the system.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS If it completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+ResetSystem (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ This function will be called when MRC is done.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Information about the notify event..
+ @param[in] Ppi The notify context.
+
+ @retval EFI_SUCCESS If the function completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ This is the callback function notified by FvFileLoader PPI, it depends on FvFileLoader PPI to load
+ the PEIM into memory.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor The context of notification.
+ @param[in] Ppi The notify PPI.
+
+ @retval EFI_SUCCESS If it completed successfully.
+
+**/
+EFI_STATUS
+EndOfPeiPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+EFI_STATUS
+EFIAPI
+FvFileLoaderPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ This function provides a blocking stall for reset at least the given number of microseconds
+ stipulated in the final argument.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] This Pointer to the local data for the interface.
+ @param[in] Microseconds Number of microseconds for which to stall.
+
+ @retval EFI_SUCCESS The function provided at least the required stall.
+
+**/
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ );
+
+/**
+ This function initialize recovery functionality by installing the recovery PPI.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS If the interface could be successfully installed.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeRecovery (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+/**
+ This function provides the implementation to properly setup both LM & PDM functionality.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS Procedure returned successfully.
+
+**/
+BOOLEAN
+EFIAPI
+IsFastBootEnabled (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+PrioritizeBootMode (
+ IN OUT EFI_BOOT_MODE *CurrentBootMode,
+ IN EFI_BOOT_MODE NewBootMode
+ );
+
+EFI_STATUS
+EFIAPI
+CapsulePpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+#endif
diff --git a/BraswellPlatformPkg/PlatformPei/PlatformPei.inf b/BraswellPlatformPkg/PlatformPei/PlatformPei.inf new file mode 100644 index 0000000000..56eddff260 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/PlatformPei.inf @@ -0,0 +1,220 @@ +## @file
+# Platform Pei Module
+#
+# This module will do chipset programming, create platforminfo hob, install
+# required mmio policy ppi.
+#
+# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformPeim
+ FILE_GUID = E95B8DF8-D2DD-45C7-8977-E470219BED51
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PeiInitPlatform
+ PI_SPECIFICATION_VERSION = 0x0001000A
+
+[Sources.common]
+ Generic/Recovery.c
+ Platform.c
+ Platform.h
+ MemoryCallback.c
+ CommonHeader.h
+ Stall.c
+ BootMode.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ ChvFspBinPkg/ChvFspBinPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ HobLib
+ MultiPlatformLib
+ MtrrLib
+ PerformanceLib
+ BaseCryptLib
+ RecoveryOemHookLib
+ GpioLib
+
+[Ppis]
+ ## PRODUCES
+ gEfiPeiStallPpiGuid
+
+ ## NOTIFY
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+ ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid
+
+ ## PRODUCES
+ gEfiPeiBootInRecoveryModePpiGuid
+
+ ## PRODUCES
+ gEfiPeiRecoveryModulePpiGuid
+
+ ## PRODUCES
+ gEfiPeiMasterBootModePpiGuid
+
+ gBoardDetectionStartPpiGuid
+
+ ## NOTIFY
+ gEfiEndOfPeiSignalPpiGuid
+[Guids]
+ ## SOMETIMES_CONSUMES ## Variable:L"Setup"
+ gEfiSetupVariableGuid
+ ## SOMETIMES_CONSUMES
+ gRecoveryOnFatIdeDiskGuid
+ ## SOMETIMES_CONSUMES
+ gRecoveryOnFatFloppyDiskGuid
+ ## SOMETIMES_CONSUMES
+ gRecoveryOnDataCdGuid
+ ## SOMETIMES_CONSUMES
+ gRecoveryOnFatUsbDiskGuid
+
+[Pcd.common]
+ ## SOMETIMES_CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
+
+ ## SOMETIMES_CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
+
+ ## SOMETIMES_CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base
+
+ ## SOMETIMES_CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
+
+ ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ ## SOMETIMES_CONSUMES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo
+
+ # CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdSdcardMode
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableHsuart0
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableHsuart1
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableAzalia
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableSata
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableXhci
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableLpe
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableDma0
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableDma1
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C0
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C1
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C2
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C3
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C4
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C5
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEnableI2C6
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdEmmcMode
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdSataInterfaceSpeed
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.ISPEnable
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.ISPPciDevConfig
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdTurboMode
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdMrcInitTsegSize
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdIgdDvmt50PreAlloc
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdApertureSize
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdGttSize
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdDvfsEnable
+
+ # CONSUMES
+ gChvFspBinPkgTokenSpaceGuid.PcdPnpSettings
+
+ gPlatformModuleTokenSpaceGuid.PcdBootToFirmwareUserInterface ## SOMETIMES_PRODUCES
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState ## SOMETIMES_CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEnableFastBoot ## SOMETIMES_CONSUMES
+
+
+[FeaturePcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatUsbDisk ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk ## CONSUMES
+
+[PcdEx]
+ ## PRODUCES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
+
+# [Hob]
+# FIRMWARE_VOLUME ## PRODUCES
+# [BootMode]
+# S3_RESUME ## PRODUCES
+#
+
diff --git a/BraswellPlatformPkg/PlatformPei/SetupVariableDefault.h b/BraswellPlatformPkg/PlatformPei/SetupVariableDefault.h new file mode 100644 index 0000000000..c1bfcb22dd --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/SetupVariableDefault.h @@ -0,0 +1,1228 @@ +/** @file
+ Driver configuration include file.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SETUP_VARIABLE_DEFAULT_H
+#define _SETUP_VARIABLE_DEFAULT_H
+#include<Guid/SetupVariable.h>
+//
+// NOTE: This is the default setup variable table
+//
+SYSTEM_CONFIGURATION gDefaultSystemConfiguration = {
+ //
+ // System ports
+ //
+ 0x0, //UINT8 Serial;
+ 0x0, //UINT8 SerialLockHide;
+
+ 0x0, //UINT8 Serial2;
+ 0x0, //UINT8 Serial2LockHide;
+
+ 0x0, //UINT8 Parallel;
+ 0x0, //UINT8 ParallelLockHide;
+
+ 0x0, //UINT8 ParallelMode;
+ 0x0, //UINT8 ParallelModeLockHide;
+
+ 0x0, //UINT8 AllUsb;
+ 0x0, //UINT8 UsbPortsLockHide;
+
+ 0x0, //UINT8 Usb2;
+ 0x0, //UINT8 Usb2LockHide;
+
+ 0x0, //UINT8 UsbLegacy;
+ 0x0, //UINT8 UsbLegacyLockHide;
+
+ //
+ // Keyboard
+ //
+ 0x0, //UINT8 Numlock;
+ 0x0, //UINT8 NumlockLockHide;
+
+ //
+ // ECIR
+ //
+ 0x0, //UINT8 ECIR;
+ 0x0, //UINT8 ECIRLockHide;
+
+ //
+ // Power State
+ //
+ 0x0, //UINT8 PowerState;
+ 0x0, //UINT8 PowerStateLockHide;
+
+ //
+ // Wake on RTC variables
+ //
+ 0x0, //UINT8 WakeOnRtcS5;
+ 0x0, //UINT8 WakeOnRtcS5LockHide;
+ 0x0, //UINT8 RTCWakeupDate;
+ 0x0, //UINT8 RTCWakeupDateLockHide;
+ 0x0, //UINT8 RTCWakeupTimeHour;
+ 0x0, //UINT8 RTCWakeupHourLockHide;
+ 0x0, //UINT8 RTCWakeupTimeMinute;
+ 0x0, //UINT8 RTCWakeupMinuteLockHide;
+ 0x0, //UINT8 RTCWakeupTimeSecond;
+ 0x0, //UINT8 RTCWakeupSecondLockHide;
+
+ //
+ // Video Adaptor
+ //
+ 0x0, //UINT8 PrimaryVideoAdaptor;
+ 0x0, //UINT8 PrimaryVideoAdaptorLockHide;
+
+ //
+ // Hybrid Graphics
+ //
+ 0x0, //UINT16 DelayAfterPwrEn;
+ 0x0, //UINT16 DelayAfterHoldReset;
+ //
+ // Chassis intrusion
+ //
+ 0x0, //UINT8 IntruderDetection;
+ 0x0, //UINT8 IntruderDetectionLockHide;
+
+ //
+ // Maximum FSB Automatic/Disable
+ //
+ 0x0, //UINT8 MaxFsb;
+ 0x0, //UINT8 MaxFsbLockHide;
+
+ //
+ // Hard Disk Pre-delay
+ //
+ 0x0, //UINT8 HddPredelay;
+ 0x0, //UINT8 HddPredelayLockHide;
+
+ //
+ // S.M.A.R.T. Mode
+ //
+ 0x0, //UINT8 SmartMode;
+ 0x0, //UINT8 SmartModeLockHide;
+
+ //
+ // ACPI Suspend State
+ //
+ 0x0, //UINT8 AcpiSuspendState;
+ 0x0, //UINT8 AcpiSuspendStateLockHide;
+
+ //
+ // PCI Latency Timer
+ //
+ 0x0, //UINT8 PciLatency;
+ 0x0, //UINT8 PciLatencyLockHide;
+
+ //
+ // Fan Control
+ //
+ 0x0, //UINT8 FanControl;
+ 0x0, //UINT8 FanControlLockHide;
+
+ //
+ // CPU Fan Control
+ //
+ 0x0, //UINT8 CpuFanControl;
+ 0x0, //UINT8 CpuFanControlLockHide;
+
+ //
+ // Lowest Fan Speed
+ //
+ 0x0, //UINT8 LowestFanSpeed;
+ 0x0, //UINT8 LowestFanSpeedLockHide;
+
+ //
+ // Processor (CPU)
+ //
+ 0x0, //UINT8 CpuFlavor;
+
+ 0x0, //UINT8 CpuidMaxValue;
+ 0x0, //UINT8 CpuidMaxValueLockHide;
+
+ 0x0, //UINT8 ExecuteDisableBit;
+ 0x0, //UINT8 ExecuteDisableBitLockHide;
+
+ //
+ // EIST or GV3 setup option
+ //
+ 0x0, //UINT8 ProcessorEistEnable;
+ 0x0, //UINT8 ProcessorEistEnableLockHide;
+
+ //
+ // C1E Enable
+ //
+ 0x0, //UINT8 ProcessorC1eEnable;
+ 0x0, //UINT8 ProcessorC1eEnableLockHide;
+
+ //
+ // Enabling CPU C-States of processor
+ //
+ 0x0, //UINT8 ProcessorCcxEnable;
+ 0x0, //UINT8 ProcessorCcxEnableLockHide;
+
+ //
+ // Package C-State Limit
+ //
+ 0x0, //UINT8 PackageCState;
+ 0x0, //UINT8 PackageCStateLockHide;
+
+ //
+ // Enable/Disable NHM C3(ACPI C2) report to OS
+ //
+ 0x0, //UINT8 OSC2Report;
+ 0x0, //UINT8 OSC2ReportLockHide;
+
+ //
+ // Enable/Disable NHM C6(ACPI C3) report to OS
+ //
+ 0x0, //UINT8 C6Enable;
+ 0x0, //UINT8 C6EnableLockHide;
+
+ //
+ // Enable/Disable NHM C7(ACPI C3) report to OS
+ //
+ 0x0, //UINT8 C7Enable;
+ 0x0, //UINT8 C7EnableLockHide;
+
+ //
+ // EIST/PSD Function select option
+ //
+ 0x0, //UINT8 ProcessorEistPsdFunc;
+ 0x0, //UINT8 ProcessorEistPsdFuncLockHide;
+
+ //
+ // CPU Active Cores and SMT
+ //
+ 0x0, //UINT8 ActiveProcessorCores;
+ 0x0, //UINT8 ActiveProcessorCoresLockHide;
+
+ //
+ // Hyper Threading
+ //
+ 0x0, //UINT8 ProcessorHyperThreadingDisable;
+ 0x0, //UINT8 ProcessorHyperThreadingDisableLockHide;
+
+ //
+ // Enabling VMX
+ //
+ 0x0, //UINT8 ProcessorVmxEnable;
+ 0x0, //UINT8 ProcessorVmxEnableLockHide;
+
+ //
+ // Enabling BIST
+ //
+ 0x0, //UINT8 ProcessorBistEnable;
+ 0x0, //UINT8 ProcessorBistEnableLockHide;
+
+ //
+ // Disabling XTPR
+ //
+ 0x0, //UINT8 ProcessorxTPRDisable;
+ 0x0, //UINT8 ProcessorxTPRDisableLockHide;
+
+ //
+ // Enabling XE
+ //
+ 0x0, //UINT8 ProcessorXEEnable;
+ 0x0, //UINT8 ProcessorXEEnableLockHide;
+
+ //
+ // Fast String
+ //
+ 0x0, //UINT8 FastStringEnable;
+ 0x0, //UINT8 FastStringEnableLockHide;
+
+ //
+ // Monitor/Mwait
+ //
+ 0x0, //UINT8 MonitorMwaitEnable;
+ 0x0, //UINT8 MonitorMwaitEnableLockHide;
+
+ //
+ // Machine Check
+ //
+ 0x0, //UINT8 MachineCheckEnable;
+ 0x0, //UINT8 MachineCheckEnableLockHide;
+
+ //
+ // Turbo mode
+ //
+ 0x0, //UINT8 TurboModeEnable;
+ 0x0, //UINT8 TurboModeEnableLockHide;
+
+ //
+ // DCA setup option
+ //
+ 0x0, //UINT8 DcaEnable;
+ 0x0, //UINT8 DcaEnableLockHide;
+
+ //
+ // DCA Prefetch Delay Value
+ //
+ 0x0, //UINT8 DcaPrefetchDelayValue;
+ 0x0, //UINT8 DcaPrefetchDelayValueLockHide;
+
+ //
+ // Hardware Prefetch
+ //
+ 0x0, //UINT8 MlcStreamerPrefetcherEnable;
+ 0x0, //UINT8 MlcStreamerPrefetcherEnableLockHide;
+
+ //
+ // Adjacent Cache Line Prefetch
+ //
+ 0x0, //UINT8 MlcSpatialPrefetcherEnable;
+ 0x0, //UINT8 MlcSpatialPrefetcherEnableLockHide;
+
+ //
+ // DCU Streamer Prefetcher
+ //
+ 0x0, //UINT8 DCUStreamerPrefetcherEnable;
+ 0x0, //UINT8 DCUStreamerPrefetcherEnableLockHide;
+
+ //
+ // DCU IP Prefetcher
+ //
+ 0x0, //UINT8 DCUIPPrefetcherEnable;
+ 0x0, //UINT8 DCUIPPrefetcherEnableLockHide;
+
+ //
+ // Enable Processor XAPIC
+ //
+ 0x0, //UINT8 ProcessorXapic;
+ 0x0, //UINT8 ProcessorXapicLockHide;
+
+ //
+ // Select BSP
+ //
+ 0x0, //UINT8 BspSelection;
+ 0x0, //UINT8 BspSelectionLockHide;
+
+ //
+ // Non-Turbo Mode Processor Core Ratio Multiplier
+ //
+ 0x0, //UINT8 ProcessorFlexibleRatio;
+ 0x0, //UINT8 ProcessorFlexibleRatioLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDC Limit Override Enable
+ //
+ 0x0, //UINT8 ProcessorTDCLimitOverrideEnable;
+ 0x0, //UINT8 ProcessorTDCLimitOverrideEnableLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDC Limit
+ //
+ 0x0, //UINT16 ProcessorTDCLimit;
+ 0x0, //UINT8 ProcessorTDCLimitLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDP Limit Override Enable
+ //
+ 0x0, //UINT8 ProcessorTDPLimitOverrideEnable;
+ 0x0, //UINT8 ProcessorTDPLimitOverrideEnableLockHide;
+
+ //
+ // Turbo-XE Mode Processor TDP Limit
+ //
+ 0x0, //UINT16 ProcessorTDPLimit;
+ 0x0, //UINT8 ProcessorTDPLimitLockHide;
+
+ //
+ // For changing UC to WB
+ //
+ 0x0, //UINT8 MTRRDefTypeUncachable;
+ 0x0, //UINT8 MTRRDefTypeUncachableLockHide;
+
+ //
+ // Virtual wire A or B
+ //
+ 0x0, //UINT8 ProcessorVirtualWireMode;
+ 0x0, //UINT8 ProcessorVirtualWireModeLockHide;
+
+ //
+ // Ext Burn in
+ //
+ 0x0, //UINT8 ExtBurnInEnable;
+ 0x0, //UINT8 ExtBurnInEnableLockHide;
+
+ //
+ // CPU Burn-in Enable 0/1 No/Yes
+ //
+ 0x0, //UINT8 CpuBurnInEnable;
+ 0x0, //UINT8 CpuBurnInEnableLockHide;
+
+ //
+ // CPU Power selection 0/1 Low/High
+ //
+ 0x0, //UINT8 CPUPow;
+ 0x0, //UINT8 CPUPowLockHide;
+
+ //
+ // VID Value to use (0-63)
+ //
+ 0x0, //UINT8 VIDVal;
+ 0x0, //UINT8 VIDValLockHide;
+
+ //
+ // BSEL Value to use (0-8)
+ //
+ 0x0, //UINT8 BSELVal;
+ 0x0, //UINT8 BSELValLockHide;
+
+ //
+ // VCore Burn-in Mode 0/1/2/3 1.500V/1.550V/1.600V/1.625V
+ //
+ 0x0, //UINT8 VCoreBurnIn;
+ 0x0, //UINT8 VCoreBurnInLockHide;
+
+ //
+ // VTT (Front Side Bus) Voltage Override
+ //
+ 0x0, //UINT8 VTtBurnIn;
+ 0x0, //UINT8 VTtBurnInLockHide;
+
+ //
+ // PCI E Burn In
+ //
+ 0x0, //UINT8 PCIeBurnIn;
+ 0x0, //UINT8 PCIeBurnInLockHide;
+
+ //
+ // FSB Override Automatic/Manual
+ //
+ 0x0, //UINT8 FsbOverride;
+ 0x0, //UINT8 FsbOverrideLockHide;
+
+ //
+ // FSB Frequency Override in MHz
+ //
+ 0x0, //UINT16 FsbFrequency;
+ 0x0, //UINT8 FsbFrequencyLockHide;
+
+ //
+ // Mailbox variables to store default, CPU Multiplier and FSB Frequency.
+ //
+ 0x0, //UINT16 DefFsbFrequency;
+
+ //
+ // Used as a CPU Voltage Status.
+ //
+ 0x0, //UINT8 VIDValStatus;
+
+ //
+ // Ecc 0/1 Disable/Enable if supported
+ //
+ 0x0, //UINT8 EccEnable;
+ 0x0, //UINT8 EccEnableLockHide;
+
+ //
+ // Memory
+ //
+ 0x0, //UINT8 MemoryMode;
+ 0x0, //UINT8 MemoryModeLockHide;
+
+ 0x0, //UINT16 MemorySpeed;
+ 0x0, //UINT8 MemorySpeedLockHide;
+
+ 0x0, //UINT8 UclkRatio;
+ 0x0, //UINT8 UclkRatioLockHide;
+
+ 0x0, //UINT8 MemoryRatio;
+ 0x0, //UINT8 MemoryRatioLockHide;
+
+ 0x0, //UINT8 MemoryTcl;
+ 0x0, //UINT8 MemoryTclLockHide;
+
+ 0x0, //UINT8 MemoryTrcd;
+ 0x0, //UINT8 MemoryTrcdLockHide;
+
+ 0x0, //UINT8 MemoryTrp;
+ 0x0, //UINT8 MemoryTrpLockHide;
+
+ 0x0, //UINT8 MemoryTras;
+ 0x0, //UINT8 MemoryTrasLockHide;
+
+ 0x0, //UINT16 MemoryTrfc;
+ 0x0, //UINT8 MemoryTrfcLockHide;
+
+ 0x0, //UINT8 MemoryTrrd;
+ 0x0, //UINT8 MemoryTrrdLockHide;
+
+ 0x0, //UINT8 MemoryTwr;
+ 0x0, //UINT8 MemoryTwrLockHide;
+
+ 0x0, //UINT8 MemoryTwtr;
+ 0x0, //UINT8 MemoryTwtrLockHide;
+
+ 0x0, //UINT8 MemoryTrtp;
+ 0x0, //UINT8 MemoryTrtpLockHide;
+
+ 0x0, //UINT8 MemoryTrc;
+ 0x0, //UINT8 MemoryTrcLockHide;
+
+ 0x0, //UINT8 MemoryTfaw;
+ 0x0, //UINT8 MemoryTfawLockHide;
+
+ 0x0, //UINT8 MemoryTcwl;
+ 0x0, //UINT8 MemoryTcwlLockHide;
+
+ 0x0, //UINT8 MemoryVoltage;
+ 0x0, //UINT8 MemoryVoltageLockHide;
+
+ //
+ // Reference Voltage Override
+ //
+ 0x0, //UINT8 DimmDqRef;
+ 0x0, //UINT8 DimmDqRefLockHide;
+ 0x0, //UINT8 DimmCaRef;
+ 0x0, //UINT8 DimmCaRefLockHide;
+
+ //
+ // Ratio Limit options for Turbo-Mode
+ //
+ 0x0, //UINT8 RatioLimit4C;
+ 0x0, //UINT8 RatioLimit4CLockHide;
+ 0x0, //UINT8 RatioLimit3C;
+ 0x0, //UINT8 RatioLimit3CLockHide;
+ 0x0, //UINT8 RatioLimit2C;
+ 0x0, //UINT8 RatioLimit2CLockHide;
+ 0x0, //UINT8 RatioLimit1C;
+ 0x0, //UINT8 RatioLimit1CLockHide;
+
+ //
+ // Port 80 decode 0/1 - PCI/LPC
+ 0x0, //UINT8 Port80Route;
+ 0x0, //UINT8 Port80RouteLockHide;
+
+ //
+ // ECC Event Logging
+ //
+ 0x0, //UINT8 EccEventLogging;
+ 0x0, //UINT8 EccEventLoggingLockHide;
+
+ //
+ // LT Technology 0/1 -> Disable/Enable
+ //
+ 0x0, //UINT8 LtTechnology;
+ 0x0, //UINT8 LtTechnologyLockHide;
+
+ //
+ // ICH Function Level Reset enable/disable
+ //
+ 0x0, //UINT8 FlrCapability;
+ 0x0, //UINT8 FlrCapabilityLockHide;
+
+ //
+ // VT-d Option
+ //
+ 0x0, //UINT8 VTdSupport;
+ 0x0, //UINT8 VTdSupportLockHide;
+
+ 0x0, //UINT8 InterruptRemap;
+ 0x0, //UINT8 InterruptRemapLockHide;
+
+ 0x0, //UINT8 Isoc;
+ 0x0, //UINT8 IsocLockHide;
+
+ 0x0, //UINT8 CoherencySupport;
+ 0x0, //UINT8 CoherencySupportLockHide;
+
+ 0x0, //UINT8 ATS;
+ 0x0, //UINT8 ATSLockHide;
+
+ 0x0, //UINT8 PassThroughDma;
+ 0x0, //UINT8 PassThroughDmaLockHide;
+
+ //
+ // IGD option
+ //
+ 0x0, //UINT8 GraphicsDriverMemorySize;
+ 0x0, //UINT8 GraphicsDriverMemorySizeLockHide;
+
+ //
+ // Hyper Threading
+ //
+ 0x0, //UINT8 ProcessorHtMode;
+ 0x0, //UINT8 ProcessorHtModeLockHide;
+
+ //
+ // IGD Aperture Size question
+ //
+ 0x2, //UINT8 IgdApertureSize;
+ 0x0, //UINT8 IgdApertureSizeLockHide;
+
+ //
+ // Boot Display Device
+ //
+ 0x0, //UINT8 BootDisplayDevice;
+ 0x0, //UINT8 BootDisplayDeviceLockHide;
+
+ //
+ // System fan speed duty cycle
+ //
+ 0x0, //UINT8 SystemFanDuty;
+ 0x0, //UINT8 SystemFanDutyLockHide;
+
+ //
+ // S3 state LED indicator
+ //
+ 0x0, //UINT8 S3StateIndicator;
+ 0x0, //UINT8 S3StateIndicatorLockHide;
+
+ //
+ // S1 state LED indicator
+ //
+ 0x0, //UINT8 S1StateIndicator;
+ 0x0, //UINT8 S1StateIndicatorLockHide;
+
+ //
+ // PS/2 Wake from S5
+ //
+ 0x0, //UINT8 WakeOnS5Keyboard;
+ 0x0, //UINT8 WakeOnS5KeyboardLockHide;
+
+ //
+ // PS2 port
+ //
+ 0x0, //UINT8 PS2;
+
+ //
+ // No VideoBeep
+ //
+ 0x0, //UINT8 NoVideoBeepEnable;
+
+ //
+ // Integrated Graphics Device
+ //
+ 0x1, //UINT8 Igd;
+
+ //
+ // Video Device select order
+ //
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, //UINT8 VideoSelectOrder[8];
+
+ // Flash update sleep delay
+ 0x0, //UINT8 FlashSleepDelay;
+ 0x0, //UINT8 FlashSleepDelayLockHide;
+
+ //
+ // Boot Display Device2
+ //
+ 0x0, //UINT8 BootDisplayDevice2;
+ 0x0, //UINT8 BootDisplayDevice2LockHide;
+
+ //
+ // Flat Panel
+ //
+ 0x0, //UINT8 EdpInterfaceType;
+ 0x0, //UINT8 EdpInterfaceTypeLockHide;
+
+ 0x0, //UINT8 LvdsInterfaceType;
+ 0x0, //UINT8 LvdsInterfaceTypeLockHide;
+
+ 0x0, //UINT8 ColorDepth;
+ 0x0, //UINT8 ColorDepthLockHide;
+
+ 0x0, //UINT8 EdidConfiguration;
+ 0x0, //UINT8 EdidConfigurationLockHide;
+
+ 0x0, //UINT8 MaxInverterPWM;
+ 0x0, //UINT8 MaxInverterPWMLockHide;
+
+ 0x0, //UINT8 PreDefinedEdidConfiguration;
+ 0x0, //UINT8 PreDefinedEdidConfigurationLockHide;
+
+ 0x0, //UINT16 ScreenBrightnessResponseTime;
+ 0x0, //UINT8 ScreenBrightnessResponseTimeLockHide;
+
+ 0x0, //UINT8 CurrentSetupProfile;
+ 0x0, //UINT8 CurrentSetupProfileLockHide;
+
+ //
+ // FSC system Variable
+ //
+ 0x0, //UINT8 CPUFanUsage;
+ 0x0, //UINT8 CPUFanUsageLockHide;
+ 0x0, //UINT16 CPUUnderSpeedthreshold;
+ 0x0, //UINT8 CPUUnderSpeedthresholdLockHide;
+ 0x0, //UINT8 CPUFanControlMode;
+ 0x0, //UINT8 CPUFanControlModeLockHide;
+ 0x0, //UINT16 Voltage12UnderVolts;
+ 0x0, //UINT8 Voltage12UnderVoltsLockHide;
+ 0x0, //UINT16 Voltage12OverVolts;
+ 0x0, //UINT8 Voltage12OverVoltsLockHide;
+ 0x0, //UINT16 Voltage5UnderVolts;
+ 0x0, //UINT8 Voltage5UnderVoltsLockHide;
+ 0x0, //UINT16 Voltage5OverVolts;
+ 0x0, //UINT8 Voltage5OverVoltsLockHide;
+ 0x0, //UINT16 Voltage3p3UnderVolts;
+ 0x0, //UINT8 Voltage3p3UnderVoltsLockHide;
+ 0x0, //UINT16 Voltage3p3OverVolts;
+ 0x0, //UINT8 Voltage3p3OverVoltsLockHide;
+ 0x0, //UINT16 Voltage2p5UnderVolts;
+ 0x0, //UINT8 Voltage2p5UnderVoltsLockHide;
+ 0x0, //UINT16 Voltage2p5OverVolts;
+ 0x0, //UINT8 Voltage2p5OverVoltsLockHide;
+ 0x0, //UINT16 VoltageVccpUnderVolts;
+ 0x0, //UINT8 VoltageVccpUnderVoltsLockHide;
+ 0x0, //UINT16 VoltageVccpOverVolts;
+ 0x0, //UINT8 VoltageVccpOverVoltsLockHide;
+ 0x0, //UINT16 Voltage5BackupUnderVolts;
+ 0x0, //UINT8 Voltage5BackupUnderVoltsLockHide;
+ 0x0, //UINT16 Voltage5BackupOverVolts;
+ 0x0, //UINT8 Voltage5BackupOverVoltsLockHide;
+ 0x0, //UINT16 VS3p3StbyUnderVolt;
+ 0x0, //UINT8 VS3p3StbyUnderVoltLockHide;
+ 0x0, //UINT16 VS3p3StbyOverVolt;
+ 0x0, //UINT8 VS3p3StbyOverVoltLockHide;
+ 0x0, //UINT8 CPUFanMinDutyCycle;
+ 0x0, //UINT8 CPUFanMinDutyCycleLockHide;
+ 0x0, //UINT8 CPUFanMaxDutyCycle;
+ 0x0, //UINT8 CPUFanMaxDutyCycleLockHide;
+ 0x0, //UINT8 CPUFanOnDutyCycle;
+ 0x0, //UINT8 CPUFanOnDutyCycleLockHide;
+ 0x0, //UINT16 CpuOverTemp;
+ 0x0, //UINT8 CpuOverTempLockHide;
+ 0x0, //UINT16 CpuControlTemp;
+ 0x0, //UINT8 CpuControlTempLockHide;
+ 0x0, //UINT16 CpuAllOnTemp;
+ 0x0, //UINT8 CpuAllOnTempLockHide;
+ 0x0, //UINT8 CpuResponsiveness;
+ 0x0, //UINT8 CpuResponsivenessLockHide;
+ 0x0, //UINT8 CpuDamping;
+ 0x0, //UINT8 CpuDampingLockHide;
+ 0x0, //UINT8 PchDamping;
+ 0x0, //UINT8 PchDampingLockHide;
+ 0x0, //UINT16 MemoryOverTemp;
+ 0x0, //UINT8 MemoryOverTempLockHide;
+ 0x0, //UINT16 MemoryControlTemp;
+ 0x0, //UINT8 MemoryControlTempLockHide;
+ 0x0, //UINT16 MemoryAllOnTemp;
+ 0x0, //UINT8 MemoryAllOnTempLockHide;
+ 0x0, //UINT8 MemoryResponsiveness;
+ 0x0, //UINT8 MemoryResponsivenessLockHide;
+ 0x0, //UINT8 MemoryDamping;
+ 0x0, //UINT8 MemoryDampingLockHide;
+ 0x0, //UINT16 VROverTemp;
+ 0x0, //UINT8 VROverTempLockHide;
+ 0x0, //UINT16 VRControlTemp;
+ 0x0, //UINT8 VRControlTempLockHide;
+ 0x0, //UINT16 VRAllOnTemp;
+ 0x0, //UINT8 VRAllOnTempLockHide;
+ 0x0, //UINT8 VRResponsiveness;
+ 0x0, //UINT8 VRResponsivenessLockHide;
+ 0x0, //UINT8 VRDamping;
+ 0x0, //UINT8 VRDampingLockHide;
+
+ 0x0, //UINT8 LvdsBrightnessSteps;
+ 0x0, //UINT8 LvdsBrightnessStepsLockHide;
+ 0x0, //UINT8 EdpDataRate;
+ 0x0, //UINT8 EdpDataRateLockHide;
+ 0x0, //UINT16 LvdsPowerOnToBacklightEnableDelayTime;
+ 0x0, //UINT8 LvdsPowerOnToBacklightEnableDelayTimeLockHide;
+ 0x0, //UINT16 LvdsPowerOnDelayTime;
+ 0x0, //UINT8 LvdsPowerOnDelayTimeLockHide;
+ 0x0, //UINT16 LvdsBacklightOffToPowerDownDelayTime;
+ 0x0, //UINT8 LvdsBacklightOffToPowerDownDelayTimeLockHide;
+ 0x0, //UINT16 LvdsPowerDownDelayTime;
+ 0x0, //UINT8 LvdsPowerDownDelayTimeLockHide;
+ 0x0, //UINT16 LvdsPowerCycleDelayTime;
+ 0x0, //UINT8 LvdsPowerCycleDelayTimeLockHide;
+
+ 0x0, //UINT8 IgdFlatPanel;
+ 0x0, //UINT8 IgdFlatPanelLockHide;
+
+ 0x0, //UINT8 SwapMode;
+ 0x0, //UINT8 SwapModeLockHide;
+
+ 0x0, //UINT8 UsbCharging;
+ 0x0, //UINT8 UsbChargingLockHide;
+
+ 0x0, //UINT8 Cstates;
+ 0x0, //UINT8 EnableC4;
+ 0x0, //UINT8 EnableC6;
+
+ 0x0, //UINT8 FastBoot;
+ 0x0, //UINT8 EfiNetworkSupport;
+ 0x0, //UINT8 PxeRom;
+
+ //
+ // Add for PpmPlatformPolicy
+ //
+ 0x0, //UINT8 EnableGv;
+ 0x0, //UINT8 EnableCx;
+ 0x0, //UINT8 EnableCxe;
+ 0x0, //UINT8 EnableTm;
+ 0x0, //UINT8 EnableProcHot;
+ 0x0, //UINT8 TStatesEnable;
+ 0x0, //UINT8 HTD;
+ 0x0, //UINT8 SingleCpu;
+ 0x0, //UINT8 BootPState;
+ 0x0, //UINT8 FlexRatio;
+ 0x0, //UINT8 FlexVid;
+ 0x0, //UINT8 QuietBoot;
+ 0x0, //UINT8 CsmControl;
+ 0x0, //UINT8 BoardId; // Need to detect Board Id during setup option for CR
+
+ 0x0, //UINT8 MinInverterPWM;
+ //
+ // Thermal Policy Values
+ //
+ 0x1, //UINT8 EnableDigitalThermalSensor;
+ 0x0, //UINT8 PassiveThermalTripPoint;
+ 0x1, //UINT8 PassiveTc1Value;
+ 0x5, //UINT8 PassiveTc2Value;
+ 0x32, //UINT8 PassiveTspValue;
+ 0x0, //UINT8 DisableActiveTripPoints;
+ 0x0, //UINT8 CriticalThermalTripPoint;
+ 0x0, //UINT8 DeepStandby;
+ 0x0, //UINT8 AlsEnable;
+ 0x0, //UINT8 IgdLcdIBia;
+ 0x1, //UINT8 LogBootTime;
+ //
+ // EM-1 related
+ //
+ 0x0, //UINT16 IaAppsRun;
+ 0x0, //UINT16 IaAppsRunCR;
+ 0x0, //UINT8 IaAppsCap;
+ 0x0, //UINT8 CapOrVoltFlag;
+ 0x0, //UINT8 BootOnInvalidBatt;
+
+ 0x0, //UINT8 IffsEnable;
+ 0x0, //UINT8 IffsOnS3RtcWake;
+ 0x0, //UINT8 IffsS3WakeTimerMin;
+ 0x0, //UINT8 IffsOnS3CritBattWake;
+ 0x0, //UINT8 IffsCritBattWakeThreshold;
+ 0x0, //UINT8 ScramblerSupport;
+ 0x0, //UINT8 SecureBoot;
+ 0x0, //UINT8 SecureBootCustomMode;
+ 0x0, //UINT8 SecureBootUserPhysicalPresent;
+ 0x0, //UINT8 CoreFreMultipSelect;
+ 0x0, //UINT8 MaxCState;
+ 0x0, //UINT8 PanelScaling;
+ 0x0, //UINT8 IgdLcdIGmchBlc;
+ 0x0, //UINT8 SecEnable;
+ 0x0, //UINT8 SecFlashUpdate;
+ 0x0, //UINT8 SecFirmwareUpdate;
+ 0x0, //UINT8 MeasuredBootEnable;
+ 0x0, //UINT8 UseProductKey;
+ //
+ // Image Signal Processor PCI Device Configuration
+ //
+ 0x0, //UINT8 ISPDevSel;
+ 0x0, //UINT8 ISPEn;
+
+ 0x0, //UINT8 Tdt;
+ 0x0, //UINT8 Recovery;
+ 0x0, //UINT8 Suspend;
+
+ 0x0, //UINT8 TdtState;
+ 0x0, //UINT8 TdtEnrolled;
+ 0x0, //UINT8 PBAEnable;
+ //
+ // ISCT Configuration
+ //
+ 0x0, //UINT8 IsctConfiguration;
+ 0x1, //UINT8 IsctNotificationControl;
+ 0x1, //UINT8 IsctWlanPowerControl;
+ 0x0, //UINT8 IsctWwanPowerControl;
+ 0x1, //UINT8 IsctSleepDurationFormat;
+ 0x1, //UINT8 IsctRFKillSupport;
+ 0x0, //UINT8 WlanNGFFCardPresence;
+ 0x0, //UINT8 WlanUHPAMCardPresence;
+ 0x0, //UINT8 PchFSAOn; //FSA control
+
+ //
+ // South Cluster Area - START
+ //
+ //
+ // Miscellaneous options
+ //
+ 0x0, //UINT8 SmbusEnabled;
+ 0x0, //UINT8 PchSirq;
+ 0x0, //UINT8 PchSirqMode;
+ 0x0, //UINT8 Hpet;
+ 0x0, //UINT8 HpetBootTime;
+ 0x0, //UINT8 EnableClockSpreadSpec;
+ 0x0, //UINT8 EnablePciClockSpreadSpec;
+ 0x0, //UINT8 EnableUsb3ClockSpreadSpec;
+ 0x0, //UINT8 EnableDisplayClockSpreadSpec;
+ 0x0, //UINT8 EnableSataClockSpreadSpec;
+ 0x1, //UINT8 StateAfterG3;
+ 0x0, //UINT8 UartInterface;
+ 0x0, //UINT8 IspLpePltClk;
+ 0x0, //UINT8 UsbDebug;
+ 0x0, //UINT8 ConfigureCfioOnSx;
+ //
+ // Security Config
+ //
+ 0x1, //UINT8 PchRtcLock;
+ 0x1, //UINT8 PchBiosLock;
+
+ //
+ // SCC Configuration
+ //
+ 0x2, //UINT8 ScceMMCEnabled;
+ 0x0, //UINT8 SccSdioEnabled;
+ 0x2, //UINT8 SccSdcardEnabled;
+ //
+ // LPSS Configuration
+ //
+ 0x1, //UINT8 GpioAcpiEnabled;
+ 0x0, //UINT16 Sdcard1p8vSwitchingDelay;
+ 0xFA, //UINT16 Sdcard3p3vDischargeDelay;
+ 0x2, //UINT8 LpssDma1Enabled;
+ 0x2, //UINT8 LpssI2C0Enabled;
+ 0x2, //UINT8 LpssI2C1Enabled;
+ 0x2, //UINT8 LpssI2C2Enabled;
+ 0x2, //UINT8 LpssI2C3Enabled;
+ 0x2, //UINT8 LpssI2C4Enabled;
+ 0x2, //UINT8 LpssI2C5Enabled;
+ 0x2, //UINT8 LpssI2C6Enabled;
+ 0x2, //UINT8 LpssDma0Enabled;
+ 0x0, //UINT8 LpssPwm0Enabled;
+ 0x0, //UINT8 LpssPwm1Enabled;
+ 0x2, //UINT8 LpssHsuart0Enabled;
+ 0x2, //UINT8 LpssHsuart1Enabled;
+ 0x0, //UINT8 LpssSpi1Enabled;
+ 0x0, //UINT8 LpssSpi2Enabled;
+ 0x0, //UINT8 LpssSpi3Enabled;
+ 0x0, //UINT8 I2CTouchAd;
+ 0x1, //UINT8 BTModule;
+ 0x1, //UINT8 RvpCameraDevSel;
+ 0x1, //UINT8 EbCameraDevSel;
+ 0x1, //UINT8 SecureNfc;
+ 0x0, //UINT8 Bcm4356;
+ 0x0, //UINT8 GpsEnable;
+
+ //
+ // Usb Config
+ //
+ 0x1, //UINT8 PchUsb30Mode;
+ 0x0, //UINT8 PchSsicEnable;
+ 0x1, //UINT8 PchUsbSsicHsRate;
+ 0x1, //UINT8 PchUsbSsicInitSequence;
+ 0x0, 0x0, //UINT8 PchUsbSsicPort[PCH_SSIC_MAX_PORTS];
+ 0x1, 0x1, //UINT8 PchUsbHsicPort[PCH_HSIC_MAX_PORTS];
+ 0x2, //UINT8 PchUsb2PhyPgEnabled;
+ 0x0, //UINT8 PchUsbOtg;
+ 0x1, //UINT8 PchUsbVbusOn; // OTG VBUS control
+
+ //
+ // Ish Config
+ //
+ 0x0, //UINT8 PchIshEnabled;
+ 0x0, //UINT8 IshDebuggerEnabled;
+
+ //
+ // SATA Config
+ //
+ 0x1, //UINT8 PchSata;
+ 0x1, //UINT8 SataInterfaceMode;
+ 0x3, //UINT8 SataInterfaceSpeed;
+ 0x1, 0x1, //UINT8 SataPort[2];
+ 0x0, 0x0, //UINT8 SataHotPlug[2];
+ 0x1, 0x1, //UINT8 SataMechanicalSw[2];
+ 0x0, 0x0, //UINT8 SataSpinUp[2];
+ 0x0, 0x0, //UINT8 SataDevSlp[2];
+ 0x0, 0x0, //UINT8 SataExternal[2];
+ 0x0, //UINT8 SataRaidR0;
+ 0x0, //UINT8 SataRaidR1;
+ 0x0, //UINT8 SataRaidR10;
+ 0x0, //UINT8 SataRaidR5;
+ 0x0, //UINT8 SataRaidIrrt;
+ 0x0, //UINT8 SataRaidOub;
+ 0x1, //UINT8 SataHddlk;
+ 0x1, //UINT8 SataLedl;
+ 0x0, //UINT8 SataRaidIooe;
+ 0x0, //UINT8 SataAlternateId;
+ 0x1, //UINT8 SataSalp;
+ 0x0, //UINT8 SataTestMode;
+
+ //
+ // PCI_EXPRESS_CONFIG, 4 ROOT PORTS
+ //
+ 0x1, 0x1, 0x1, 0x1, //UINT8 PcieRootPortEn[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortAspm[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortURE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortFEE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortNFE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortCEE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortSFE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortSNE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortSCE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x1, 0x1, 0x1, 0x1, //UINT8 PcieRootPortPMCE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortESE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortHPE[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortSpeed[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortTHS[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x3, 0x3, 0x3, 0x3, //UINT8 PcieRootPortL1SubStates[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortNccSsc[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieRootPortTxEqDeemphSelection[PCH_PCIE_MAX_ROOT_PORTS];
+
+ //
+ // PCI Bridge Resources
+ //
+ 0x0, 0x0, 0x0, 0x0, //UINT8 PcieExtraBusRsvd[PCH_PCIE_MAX_ROOT_PORTS];
+ 0xA, 0xA, 0xA, 0xA, //UINT8 PcieMemRsvd[PCH_PCIE_MAX_ROOT_PORTS];
+ 0x4, 0x4, 0x4, 0x4, //UINT8 PcieIoRsvd[PCH_PCIE_MAX_ROOT_PORTS];
+
+ //
+ // PCI Express S0ix Config
+ //
+ 0x1, //UINT8 PcieS0iX;
+ 0x2, //UINT8 D0S0IxPolicy;
+ 0x1, //UINT8 ClkReqEnable;
+ 0x0, //UINT8 ClkReq;
+ 0x2, //UINT8 LtrLatencyScale;
+ 0x96, //UINT8 LtrLatencyValue;
+
+ //
+ // Audio Configuration
+ //
+ 0x0, //UINT8 PchLpeEnabled;
+ 0x1, //UINT8 PchAzalia;
+ 0x1, //UINT8 AzaliaVCiEnable;
+ 0x0, //UINT8 AzaliaDs;
+ 0x1, //UINT8 AzaliaPme;
+ 0x1, //UINT8 HdmiCodec;
+ 0x1, //UINT8 HdmiCodecPortB;
+ 0x1, //UINT8 HdmiCodecPortC;
+ 0x1, //UINT8 HdmiCodecPortD;
+ //
+ // South Cluster Area - END
+ //
+
+ 0x2, //UINT8 GTTSize;
+ //
+ // DVMT5.0 Graphic memory setting
+ //
+ 0x2, //UINT8 IgdDvmt50PreAlloc;
+ 0x2, //UINT8 IgdDvmt50TotalAlloc;
+ 0x0, //UINT8 IgdTurboEnabled;
+ 0x0, //UINT8 EnableRenderStandby;
+ 0x1, //UINT8 GOPEnable;
+ 0x5, //UINT8 GOPBrightnessLevel; // Gop Brightness level
+ 0x0, //UINT8 PanelConfig;
+ 0x0, //UINT8 PanelVendor;
+ 0x1, //UINT8 PavpMode;
+ 0x0, //UINT8 EnablePR3;
+ 0x0, //UINT8 Wopcmsz;
+ 0x0, //UINT8 UnsolicitedAttackOverride;
+
+ 0x0, //UINT8 SeCOpEnable;
+ 0x0, //UINT8 SeCModeEnable;
+ 0x0, //UINT8 SeCEOPEnable;
+ 0x0, //UINT8 SeCEOPDone;
+
+ 0x2, //UINT8 LidStatus;
+ 0x0, //UINT8 PowerMeterLock;
+ 0x0, //UINT8 EuControl;
+ 0x0, //UINT8 SdpProfile; // DPTF: an enumeration for Brand Strings.
+ 0x0, //UINT8 CameraSelect;
+ 0x0, //UINT8 F22Rework;
+ 0x0, //UINT8 EnableDptf; // Option to enable/disable DPTF
+ 0x0, //UINT16 ProcCriticalTemp; // Processor critical temperature
+ 0x0, //UINT16 ProcPassiveTemp; // Processor passive temperature
+
+ 0x0, //UINT16 ActiveThermalTripPointSA; // Processor active temperature
+ 0x0, //UINT16 CriticalThermalTripPointSA; // Processor critical temperature
+ 0x0, //UINT16 CR3ThermalTripPointSA; // Processor CR3 temperature
+ 0x0, //UINT16 HotThermalTripPointSA; // Processor Hot temperature
+ 0x0, //UINT16 PassiveThermalTripPointSA; // Processor passive temperature
+
+ 0x0, //UINT16 GenericActiveTemp0; // Active temperature value for generic sensor0 participant
+ 0x0, //UINT16 GenericCriticalTemp0; // Critical temperature value for generic sensor0 participant
+ 0x0, //UINT16 GenericCR3Temp0; // CR3 temperature value for generic sensor0 participant
+ 0x0, //UINT16 GenericHotTemp0; // Hot temperature value for generic sensor0 participant
+ 0x0, //UINT16 GenericPassiveTemp0; // Passive temperature value for generic sensor0 participant
+ 0x0, //UINT16 GenericActiveTemp1; // Active temperature value for generic sensor1 participant
+ 0x0, //UINT16 GenericCriticalTemp1; // Critical temperature value for generic sensor1 participant
+ 0x0, //UINT16 GenericCR3Temp1; // CR3 temperature value for generic sensor1 participant
+ 0x0, //UINT16 GenericHotTemp1; // Hot temperature value for generic sensor1 participant
+ 0x0, //UINT16 GenericPassiveTemp1; // Passive temperature value for generic sensor1 participant
+ 0x0, //UINT16 GenericActiveTemp2; // Active temperature value for generic sensor2 participant
+ 0x0, //UINT16 GenericCriticalTemp2; // Critical temperature value for generic sensor2 participant
+ 0x0, //UINT16 GenericCR3Temp2; // CR3 temperature value for generic sensor2 participant
+ 0x0, //UINT16 GenericHotTemp2; // Hot temperature value for generic sensor2 participant
+ 0x0, //UINT16 GenericPassiveTemp2; // Passive temperature value for generic sensor2 participant
+ 0x0, //UINT16 GenericCriticalTemp3; // Critical temperature value for generic sensor3 participant
+ 0x0, //UINT16 GenericPassiveTemp3; // Passive temperature value for generic sensor3 participant
+ 0x0, //UINT16 GenericCriticalTemp4; // Critical temperature value for generic sensor3 participant
+ 0x0, //UINT16 GenericPassiveTemp4; // Passive temperature value for generic sensor3 participant
+ 0x0, //UINT8 Clpm; // Current low power mode
+ 0x0, //UINT8 SuperDebug; // DPTF Super debug option
+ 0x0, //UINT32 LPOEnable; // DPTF: Instructs the policy to use Active Cores if they are available. If this option is set to 0, then policy does not use any active core controls ?even if they are available
+ 0x0, //UINT32 LPOStartPState; // DPTF: Instructs the policy when to initiate Active Core control if enabled. Returns P state index.
+ 0x0, //UINT32 LPOStepSize; // DPTF: Instructs the policy to take away logical processors in the specified percentage steps
+ 0x0, //UINT32 LPOPowerControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P0 or when power control is applied. 1 ?SMT Off lining 2- Core Off lining
+ 0x0, //UINT32 LPOPerformanceControlSetting; // DPTF: Instructs the policy whether to use Core offliing or SMT offlining if Active core control is enabled to be used in P1 or when performance control is applied.1 ?SMT Off lining 2- Core Off lining
+ 0x0, //UINT8 EnableDppm; // DPTF: Controls DPPM Policies (enabled/disabled)
+ 0x0, //UINT8 DptfProcessor;
+ 0x0, //UINT8 DptfSysThermal0;
+ 0x0, //UINT8 DptfSysThermal1;
+ 0x0, //UINT8 DptfSysThermal2;
+ 0x0, //UINT8 DptfSysThermal3;
+ 0x0, //UINT8 DptfSysThermal4;
+ 0x0, //UINT8 DptfChargerDevice;
+ 0x0, //UINT8 DptfDisplayDevice;
+ 0x0, //UINT8 DptfSocDevice;
+ 0x0, //UINT8 BidirectionalProchotEnable;
+ 0x0, //UINT8 ThermalMonitoring;
+ 0x0, //UINT8 ThermalMonitoringHot;
+ 0x0, //UINT8 ThermalMonitoringSystherm0Hot;
+ 0x0, //UINT8 ThermalMonitoringSystherm1Hot;
+ 0x0, //UINT8 ThermalMonitoringSystherm2Hot;
+ 0x0, //UINT8 DisplayHighLimit;
+ 0x0, //UINT8 DisplayLowLimit;
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, //UINT8 AmbientConstants[6];
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, //UINT8 AmbientConstantSign[6];
+ 0x0, //UINT8 AmbientTripPointChange; // DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)
+ 0x1, //UINT8 DptfAllowHigherPerformance; // DPTF: Allow higher performance on AC/USB - (Enable/Disable)
+ 0x0, //UINT8 DptfWwanDevice; // DPTF: Presence of WWAN Device
+ 0x300, //UINT32 DptfWwanCrt; // DPTF: WWAN critical temperature
+ 0x0, //UINT32 DptfWwanPsv; // DPTF: WWAN Passive Temperature
+ 0x0, //UINT8 EnablePassivePolicy; // DPTF: Passive Policy enable/disable
+ 0x0, //UINT8 EnableCriticalPolicy; // DPTF: Critical Policy enable/disable
+ 0x0, //UINT8 EnableActivePolicy; // DPTF: Active Policy enable/disable
+ 0x0, //UINT8 PmicEnable;
+ 0x3, //UINT8 S0ix;
+ 0x1, //UINT8 TSEGSizeSel;
+ 0x0, //UINT8 ACPIMemDbg;
+ 0x0, //UINT8 ExISupport;
+ 0x0, //UINT8 BatteryChargingSolution; // 0-non ULPMC 1-ULPMC
+
+ 0x0, //UINT8 PnpSettings;
+ 0x0, //UINT8 MfgMode;
+ 0x0, //UINT8 CRIDSettings;
+ 0x0, //UINT8 ULPMCFWLock;
+ 0x0, //UINT8 PssEnabled;
+ 0x0, //UINT8 PmWeights;
+ 0x0, //UINT8 PdmEnable;
+ 0x0, //UINT8 PDMConfig;
+ 0x0, //UINT16 LmMemSize;
+ 0x0, //UINT8 PunitBIOSConfig;
+ 0x0, //UINT8 LpssSdioMode;
+ 0x0, //UINT8 ENDBG2;
+ 0x0, //UINT8 IshPullUp;
+ 0x0, //UINT8 TristateLpc;
+ 0x0, //UINT8 UsbXhciLpmSupport;
+ 0x0, //UINT8 VirtualKbEnable;
+ 0x0, //UINT8 SlpS0ixN;
+ 0x0, //UINT8 EnableAESNI;
+ 0x0, //UINT8 SecureErase;
+
+ //
+ // Memory Config Tools
+ //
+ 0x0, //UINT8 MrcEvRMT;
+ 0x0, //UINT8 MrcCmdRMT;
+ 0x0, //UINT8 MrcDvfsEnable;
+ 0x0, //UINT8 MrcFreqASel;
+ 0x0, //UINT8 MrcFreqBSel;
+ 0x0, //UINT8 MrcLPDDR3ChipSel;
+ 0x0, //UINT8 MrcChannelSel;
+ 0x0, //UINT8 MrcDynamicSr;
+ 0x0, //UINT8 MrcChannelSel_3_0;
+ 0x0, //UINT8 MrcChannelSel_4;
+ 0x0, //UINT8 MrcAutoDetectDram;
+ 0x0, //UINT8 Sku;
+ 0x4, //UINT8 MrcPm5Enable;
+ 0x0, //UINT8 MrcBankAddressHashingEnable;
+ 0x0, //UINT8 MrcRankSelInterleave;
+ 0x0, //UINT8 MrcConfigChanged;
+ 0x0, //UINT8 MrcDdrType;
+ 0x0, //UINT8 MrcDdr2nMode;
+ 0x0, //UINT8 MrcRxPwrTrainingDisable;
+ 0x0, //UINT8 MrcTxPwrTrainingDisable;
+ 0x0, //UINT8 MrcFastBootDisable;
+ 0x0, //UINT8 MrcScramblerDisable;
+ 0x0, //UINT8 MrcSpeedGrade;
+ 0x0, //UINT8 MrcLPDDR3DeviceDensity;
+ 0x0, //UINT8 MrcDebugMsgLevel;
+ 0x0, //UINT8 DrpLockDisable;
+ 0x0, //UINT8 ReutLockDisable;
+ 0x0, //UINT8 RhPrevention;
+
+ 0x0, //UINT8 MmioSize;
+ 0x0, //UINT8 DroidBoot;
+ 0x0, //UINT8 AndroidBoot;
+ 0x0, //UINT8 Ellensburg;
+ 0x0, //UINT8 CriticalBatteryLimit;
+ 0x0, //UINT8 CriticalBatteryLimitFeature;
+ 0x0, //UINT8 EmmcDriverMode;
+ 0x0, //UINT8 EmmcRxTuningEnable;
+ 0x0, //UINT8 EmmcTxTuningEnable;
+
+ 0x0, //UINT8 SAR1;
+
+ 0x0, //UINT8 DisableCodec262;
+ 0x0, //UINT8 PcieDynamicGating; // Need PMC enable it first from PMC 0x3_12 MCU 318.
+ 0x0, //UINT8 VirtualButtonEnable;
+ 0x0, //UINT8 RotationLock;
+ 0x0, //UINT8 ConvertibleState;
+ 0x0, //UINT8 DockIndicator;
+ 0x0, //UINT8 WIFIModule;
+ 0x0, //UINT8 SvidConfig;
+ 0x0, //UINT8 PciExpNative;
+ 0x0, //UINT8 OsSelection;
+ 0x0, //UINT8 PlatformDirectOsSelect; //If set to 1 (TRUE), platform method (GPI on Cherry Hill) will be used to select OS.
+ //If set to 0 (FALSE), OS selection option in setup menu will be used to select OS.
+
+ 0x0, //UINT8 MipiDsi;
+ 0x0, //UINT8 AndroidSBIntegration;
+ 0x0, //UINT8 AcpiDevNodeDis;
+ 0x0, //UINT8 AcpiModemSel;
+
+ //
+ // SPID config region
+ //
+ 0x0, //UINT8 SPIDAutoDetect;
+ 0x0, //UINT16 SPIDCustomerID;
+ 0x0, //UINT16 SPIDVendorID;
+ 0x0, //UINT16 SPIDDeviceManufacturerID;
+ 0x0, //UINT16 SPIDPlatformFamilyID;
+ 0x0, //UINT16 SPIDProductLineID;
+ 0x0, //UINT16 SPIDHardwareID;
+ 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, //UINT8 SPIDFru[20];
+ 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
+ //
+ // OEM1 table
+ //
+ 0x0, //UINT8 BatIdDbiBase;
+ 0x0, //UINT8 BatIdAnlgBase;
+ 0x0, //UINT16 VBattFreqLimit;
+ 0x4, //UINT8 CapFreqIdx;
+ 0x0, //UINT8 BTHStatus;
+ 0x0, //UINT8 AudioCodecSuppport;
+ 0x0, //UINT8 ChargingEnable;
+ 0x0, //UINT8 ChargingLpmEnable;
+ 0x0, //UINT16 Str2TspValue;
+ 0x0, //UINT8 VBIOS5f35h;
+ 0x0, //UINT8 VBIOS5f40h;
+ 0x0, //UINT8 Backlight;
+ 0x0, //UINT8 PunitPwrConfigDisable;
+ 0x0, //UINT8 FlashLessMdm;
+ 0x0, //UINT8 EnableMSCustomSdbusDriver;
+ 0x0, //UINT8 XdbGpioTrst;
+ 0x0, //UINT8 FirstBootIndicator;
+ 0x0, //UINT8 ConnectAllCtrlsFlag;
+ 0x0, //UINT8 EnterDnxFastBoot;
+ 0x0, //UINT8 ToggleSelfClkDisabling;
+ 0x0, //UINT8 GPSHIDSelection;
+ 0x0 //UINT8 HighPerfMode;
+
+};
+
+#endif // #ifndef _SETUP_VARIABLE_DEFAULT_H
diff --git a/BraswellPlatformPkg/PlatformPei/Stall.c b/BraswellPlatformPkg/PlatformPei/Stall.c new file mode 100644 index 0000000000..ce89440e37 --- /dev/null +++ b/BraswellPlatformPkg/PlatformPei/Stall.c @@ -0,0 +1,85 @@ +/** @file
+ Produce Stall Ppi.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CommonHeader.h"
+#include "PlatformBaseAddresses.h"
+#include "PchRegs.h"
+
+/**
+ Waits for at least the given number of microseconds.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] This PPI instance structure.
+ @param[in] Microseconds Desired length of time to wait.
+
+ @retval EFI_SUCCESS If the desired amount of time was passed.
+
+**/
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ )
+{
+ UINTN Ticks;
+ UINTN Counts;
+ UINT32 CurrentTick;
+ UINT32 OriginalTick;
+ UINT32 RemainingTick;
+
+ if (Microseconds == 0) {
+ return EFI_SUCCESS;
+ }
+
+ OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);
+ OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);
+ CurrentTick = OriginalTick;
+
+ //
+ // The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks
+ //
+ Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
+
+ //
+ // The loops needed for timer overflow
+ //
+ Counts = (UINTN) RShiftU64 ((UINT64)Ticks, 24);
+
+ //
+ // Remaining clocks within one loop
+ //
+ RemainingTick = Ticks & 0xFFFFFF;
+
+ //
+ // Do not intend to use TMROF_STS bit of register PM1_STS, because this add extra
+ // one I/O operation, and may generate SMI
+ //
+ while (Counts != 0) {
+ CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
+ if (CurrentTick <= OriginalTick) {
+ Counts--;
+ }
+ OriginalTick = CurrentTick;
+ }
+
+ while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) {
+ OriginalTick = CurrentTick;
+ CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;
+ }
+
+ return EFI_SUCCESS;
+}
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