diff options
| author | Guo Mang <mang.guo@intel.com> | 2016-08-03 10:42:15 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2016-08-04 10:31:56 +0800 |
| commit | 5dd29bdf5181c66bd56ec4d0ec9da072007b131c (patch) | |
| tree | bd20f3d0fb495e9e805cd20d62af44c29f260019 | |
| parent | 0b1e22f217a82af464e89cb491434bf7631a625d (diff) | |
| download | edk2-platforms-5dd29bdf5181c66bd56ec4d0ec9da072007b131c.tar.xz | |
BraswellPlatformPkg: Restructure code in Common/PlatformPei directory
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
19 files changed, 2176 insertions, 623 deletions
diff --git a/BraswellPlatformPkg/Common/PlatformPei/CommonHeader.h b/BraswellPlatformPkg/Common/PlatformPei/CommonHeader.h deleted file mode 100644 index 23b2ac4715..0000000000 --- a/BraswellPlatformPkg/Common/PlatformPei/CommonHeader.h +++ /dev/null @@ -1,63 +0,0 @@ -/** @file
- Common header file shared by all source files.
- This file includes package header files, library classes and protocol, PPI & GUID definitions.
-
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __COMMON_HEADER_H_
-#define __COMMON_HEADER_H_
-
-#include <FrameworkPei.h>
-#include <IndustryStandard/SmBus.h>
-#include <IndustryStandard/Pci22.h>
-#include <Ppi/AtaController.h>
-#include <Guid/Capsule.h>
-#include <Ppi/Cache.h>
-#include <Ppi/MasterBootMode.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Guid/RecoveryDevice.h>
-#include <Ppi/ReadOnlyVariable2.h>
-#include <Ppi/FvLoadFile.h>
-#include <Ppi/DeviceRecoveryModule.h>
-#include <Ppi/Capsule.h>
-#include <Ppi/Reset.h>
-#include <Ppi/Stall.h>
-#include <Ppi/BootInRecoveryMode.h>
-#include <Guid/FirmwareFileSystem2.h>
-#include <Ppi/MemoryDiscovered.h>
-#include <Ppi/RecoveryModule.h>
-#include <Ppi/Smbus2.h>
-#include <Ppi/FirmwareVolumeInfo.h>
-#include <Ppi/EndOfPeiPhase.h>
-#include <Library/DebugLib.h>
-#include <Library/PeimEntryPoint.h>
-#include <Library/BaseLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/HobLib.h>
-#include <Library/PciCf8Lib.h>
-#include <Library/IoLib.h>
-#include <Library/PciLib.h>
-#include <Library/ReportStatusCodeLib.h>
-#include <Library/PcdLib.h>
-#include <Library/SmbusLib.h>
-#include <Library/TimerLib.h>
-#include <Library/PrintLib.h>
-#include <Library/ResetSystemLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PerformanceLib.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/MtrrLib.h>
-#include <Library/RecoveryOemHookLib.h>
-
-#endif
diff --git a/BraswellPlatformPkg/Common/PlatformPei/MemoryCallback.c b/BraswellPlatformPkg/Common/PlatformPei/MemoryCallback.c deleted file mode 100644 index c212383a34..0000000000 --- a/BraswellPlatformPkg/Common/PlatformPei/MemoryCallback.c +++ /dev/null @@ -1,219 +0,0 @@ -/** @file
- This file includes a memory call back function notified when MRC is done,
- following action is performed in this file,
- 1. ICH initialization after MRC.
- 2. SIO initialization.
- 3. Install ResetSystem and FinvFv PPI.
- 4. Set MTRR for PEI
- 5. Create FV HOB and Flash HOB
-
- Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "CommonHeader.h"
-#include "Platform.h"
-#include <Ppi/Cache.h>
-#include <Library/BaseCryptLib.h>
-#include <Guid/PlatformInfo.h>
-#include "ChvAccess.h"
-
-/**
- This function will be called when MRC is done.
-
- @param[in] PeiServices General purpose services available to every PEIM.
- @param[in] NotifyDescriptor Information about the notify event..
- @param[in] Ppi The notify context.
-
- @retval EFI_SUCCESS If the function completed successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-MemoryDiscoveredPpiNotifyCallback (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
- UINT32 Pages;
- VOID* Memory;
- UINTN Size;
- EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
- UINT32 FvAlignment;
-
- Status = (*PeiServices)->GetBootMode (
- (const EFI_PEI_SERVICES **)PeiServices,
- &BootMode
- );
-
- if (BootMode == BOOT_IN_RECOVERY_MODE) {
- //
- // Install Recovery PPI
- //
- Status = InitializeRecovery ((EFI_PEI_SERVICES **)PeiServices);
- ASSERT_EFI_ERROR (Status);
-
- }
-
- if (BootMode != BOOT_ON_S3_RESUME) {
- Size = PcdGet32(PcdFlashFvRecovery2Size);
- if (Size > 0) {
- Pages= (Size + 0xFFF)/0x1000;
-
- Memory = AllocatePages ( Pages );
- CopyMem(Memory , (VOID *) PcdGet32(PcdFlashFvRecovery2Base) , Size);
-
- //
- // We don't verify just load
- //
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *) Memory,
- PcdGet32 (PcdFlashFvRecovery2Size),
- NULL,
- NULL
- );
- }
-
- if (BootMode != BOOT_IN_RECOVERY_MODE){
- Size = PcdGet32(PcdFlashFvMainSize);
- Pages= (Size + 0xFFF)/0x1000;
-
- FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32(PcdFlashFvMainBase);
-
- //
- // Check the FV alignment
- //
- if ((FvHeader->Attributes & EFI_FVB2_WEAK_ALIGNMENT) != EFI_FVB2_WEAK_ALIGNMENT) {
- //
- // Get FvHeader alignment
- //
- FvAlignment = 1 << ((FvHeader->Attributes & EFI_FVB2_ALIGNMENT) >> 16);
- //
- // FvAlignment must be greater than or equal to 8 bytes of the minimum FFS alignment value.
- //
- if (FvAlignment < 8) {
- FvAlignment = 8;
- }
- Memory = AllocateAlignedPages (Pages, FvAlignment);
- } else {
- Memory = AllocatePages ( Pages );
- }
- CopyMem(Memory , (VOID *) PcdGet32(PcdFlashFvMainBase) , Size);
-
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *) Memory,
- PcdGet32 (PcdFlashFvMainSize),
- NULL,
- NULL
- );
- }
- }
-
- if (BootMode == BOOT_ON_S3_RESUME) {
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *) (UINTN) (PcdGet32 (PcdFlashFvRecovery2Base)),
- PcdGet32 (PcdFlashFvRecovery2Size),
- NULL,
- NULL
- );
- }
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-EndOfPeiPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- )
-{
- EFI_STATUS Status;
- EFI_BOOT_MODE BootMode;
- UINTN Instance;
- EFI_PEI_FV_HANDLE VolumeHandle;
- EFI_FV_INFO VolumeInfo;
- EFI_PEI_FILE_HANDLE FileHandle;
- EFI_FV_FILE_INFO FileInfo;
- UINTN FfsCount;
- UINTN FvImageCount;
- Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
- ASSERT_EFI_ERROR (Status);
- //
- // Check whether FVMAIN is compressed. If not, we will publish fv hob here in Normal Boot..
- //
- //
- // Determine if Main FV is only composed of FV Image files
- //
- if (BootMode != BOOT_ON_S3_RESUME && BootMode != BOOT_IN_RECOVERY_MODE) {
- Instance = 0;
- while (TRUE) {
- //
- // Traverse all firmware volume instances to find FV Main instance
- //
- Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
- if (EFI_ERROR (Status)) {
- break;
- }
- Status = PeiServicesFfsGetVolumeInfo(VolumeHandle, &VolumeInfo);
- if (EFI_ERROR (Status)) {
- Instance++;
- continue;
- }
-
- if (VolumeInfo.FvSize != PcdGet32 (PcdFlashFvMainSize)) {
- Instance++;
- continue;
- }
-
- //
- // Count total number of FFS files and number of FV Image files in FV Main.
- //
- FileHandle = NULL;
- FfsCount = 0;
- FvImageCount = 0;
- while (TRUE) {
- Status = PeiServicesFfsFindNextFile (EFI_FV_FILETYPE_ALL, VolumeHandle, &FileHandle);
- if (EFI_ERROR (Status)) {
- break;
- }
- FfsCount++;
- Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);
- if (EFI_ERROR (Status)) {
- continue;
- }
- if (FileInfo.FileType == EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE) {
- FvImageCount++;
- }
- }
- //
- // If number if FFS files is not the same as the number of FV Image files,
- // then publish HOB for FV Main so it is available for use in the DXE Phase.
- //
- if (FfsCount != FvImageCount) {
- BuildFvHob (
- (UINTN)VolumeInfo.FvStart,
- VolumeInfo.FvSize
- );
- DEBUG ((EFI_D_INFO, "FVMAIN Fv Hob Built, BaseAddress=0x%x, Size=%x\n", VolumeInfo.FvStart, VolumeInfo.FvSize));
- }
- break;
- }
- }
-
- return Status;
-}
diff --git a/BraswellPlatformPkg/Common/PlatformPei/Platform.c b/BraswellPlatformPkg/Common/PlatformPei/Platform.c deleted file mode 100644 index bd8cb33e67..0000000000 --- a/BraswellPlatformPkg/Common/PlatformPei/Platform.c +++ /dev/null @@ -1,316 +0,0 @@ -/** @file
- This PEIM initialize platform for MRC, following action is performed,
- 1. Initialize GMCH
- 2. Detect boot mode
- 3. Detect video adapter to determine whether we need pre-allocated memory
- 4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.
- This file contains the main entry point of the PEIM.
-
- Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "CommonHeader.h"
-#include "Platform.h"
-#include "PlatformBaseAddresses.h"
-#include "PchRegs.h"
-#include <Guid/PlatformInfo.h>
-#include "ChvAccess.h"
-#include <Library/GpioLib.h>
-#include <Guid/Chv2Variable.h>
-#include <Ppi/ChvPlatformPolicyPpi.h>
-#include <Ppi/BoardDetection.h>
-#include <Guid/SetupVariable.h>
-#include "SetupVariableDefault.h"
-
-#ifndef EC_BASE
-#define EC_BASE ((UINTN)PcdGet64(PcdPciExpressBaseAddress))
-#endif
-
-#ifndef MmPciAddress
-#define MmPciAddress(Segment, Bus, Device, Function, Register) \
- ((UINTN) EC_BASE + \
- (UINTN) (Bus << 20) + \
- (UINTN) (Device << 15) + \
- (UINTN) (Function << 12) + \
- (UINTN) (Register) \
- )
-#endif
-
-//
-// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory
-//
-
-EFI_STATUS
-EFIAPI
-Stall (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN CONST EFI_PEI_STALL_PPI *This,
- IN UINTN Microseconds
- );
-
-static EFI_PEI_STALL_PPI mStallPpi = {
- PEI_STALL_RESOLUTION,
- Stall
-};
-
-static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gEfiPeiStallPpiGuid,
- &mStallPpi
- }
-};
-
-EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
- {
- (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiPeiMemoryDiscoveredPpiGuid,
- MemoryDiscoveredPpiNotifyCallback
- }
-};
-
-EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gEfiEndOfPeiSignalPpiGuid,
- EndOfPeiPpiNotifyCallback
- }
-};
-static EFI_PEI_PPI_DESCRIPTOR mBoardDetectionStartPpi[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gBoardDetectionStartPpiGuid,
- NULL
- }
-};
-STATIC
-EFI_STATUS
-CheckSetupVarItem (
- IN SYSTEM_CONFIGURATION *SystemConfiguration
- )
-{
- DEBUG ((EFI_D_INFO, "CheckSetupVarItem(): entry \n"));
- if (SystemConfiguration->TurboModeEnable > 1)
- SystemConfiguration->TurboModeEnable = PcdGet8(PcdTurboMode);
- //
- // South Complex
- //
- if (SystemConfiguration->SccSdcardEnabled > 2)
- SystemConfiguration->SccSdcardEnabled = PcdGet8(PcdSdcardMode);
- if (SystemConfiguration->LpssHsuart0Enabled > 2)
- SystemConfiguration->LpssHsuart0Enabled = PcdGet8(PcdEnableHsuart0);
- if (SystemConfiguration->LpssHsuart1Enabled > 2)
- SystemConfiguration->LpssHsuart1Enabled = PcdGet8(PcdEnableHsuart1);
- if (SystemConfiguration->PchAzalia > 1)
- SystemConfiguration->PchAzalia = PcdGet8(PcdEnableAzalia);
- if (SystemConfiguration->PchSata > 1)
- SystemConfiguration->PchSata = PcdGet8(PcdEnableSata);
- if (SystemConfiguration->PchUsb30Mode > 1)
- SystemConfiguration->PchUsb30Mode = PcdGet8(PcdEnableXhci);
- if (SystemConfiguration->PchLpeEnabled > 2)
- SystemConfiguration->PchLpeEnabled = PcdGet8(PcdEnableLpe);
- if (SystemConfiguration->LpssDma0Enabled > 2)
- SystemConfiguration->LpssDma0Enabled = PcdGet8(PcdEnableDma0);
- if (SystemConfiguration->LpssDma1Enabled > 2)
- SystemConfiguration->LpssDma1Enabled = PcdGet8(PcdEnableDma1);
- if (SystemConfiguration->LpssI2C0Enabled > 2)
- SystemConfiguration->LpssI2C0Enabled = PcdGet8(PcdEnableI2C0);
- if (SystemConfiguration->LpssI2C1Enabled > 2)
- SystemConfiguration->LpssI2C1Enabled = PcdGet8(PcdEnableI2C1);
- if (SystemConfiguration->LpssI2C2Enabled > 2)
- SystemConfiguration->LpssI2C2Enabled = PcdGet8(PcdEnableI2C2);
- if (SystemConfiguration->LpssI2C3Enabled > 2)
- SystemConfiguration->LpssI2C3Enabled = PcdGet8(PcdEnableI2C3);
- if (SystemConfiguration->LpssI2C4Enabled > 2)
- SystemConfiguration->LpssI2C4Enabled = PcdGet8(PcdEnableI2C4);
- if (SystemConfiguration->LpssI2C5Enabled > 2)
- SystemConfiguration->LpssI2C5Enabled = PcdGet8(PcdEnableI2C5);
- if (SystemConfiguration->LpssI2C6Enabled > 2)
- SystemConfiguration->LpssI2C6Enabled = PcdGet8(PcdEnableI2C6);
- if (SystemConfiguration->ScceMMCEnabled > 2)
- SystemConfiguration->ScceMMCEnabled = PcdGet8(PcdEmmcMode);
- if (SystemConfiguration->SataInterfaceSpeed > 3)
- SystemConfiguration->SataInterfaceSpeed = PcdGet8(PcdSataInterfaceSpeed);
- if (SystemConfiguration->ISPEn > 1)
- SystemConfiguration->ISPEn = PcdGet8(ISPEnable);
- if (SystemConfiguration->ISPDevSel > 2)
- SystemConfiguration->ISPDevSel = PcdGet8(ISPPciDevConfig);
- if (SystemConfiguration->MrcDvfsEnable > 1)
- SystemConfiguration->MrcDvfsEnable = PcdGet8(PcdDvfsEnable);
- if (SystemConfiguration->PnpSettings > 5)
- SystemConfiguration->PnpSettings = PcdGet8(PcdPnpSettings);
-
- //
- // North Complex
- //
- if (SystemConfiguration->GTTSize > 2)
- SystemConfiguration->GTTSize = PcdGet8(PcdGttSize);
-
- if (SystemConfiguration->IgdApertureSize > 3)
- SystemConfiguration->IgdApertureSize = PcdGet8(PcdApertureSize);
-
- if (SystemConfiguration->IgdDvmt50PreAlloc > 16)
- SystemConfiguration->IgdDvmt50PreAlloc = PcdGet8(PcdIgdDvmt50PreAlloc);
-
-
- DEBUG ((EFI_D_INFO, "CheckSetupVarItem(): exit \n"));
-
- return EFI_SUCCESS;
-}
-
-EFI_STATUS
-GetSetupVariable (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN SYSTEM_CONFIGURATION *SystemConfiguration
- )
-{
- UINTN VariableSize;
- EFI_STATUS Status;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
-
- VariableSize = sizeof (SYSTEM_CONFIGURATION);
- ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
-
- Status = (*PeiServices)->LocatePpi (PeiServices,
- &gEfiPeiReadOnlyVariable2PpiGuid,
- 0,
- NULL,
- &Variable
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Use normal setup default from NVRAM variable,
- // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
- //
- VariableSize = sizeof(SYSTEM_CONFIGURATION);
- Status = Variable->GetVariable (Variable,
- L"Setup",
- &gEfiSetupVariableGuid,
- NULL,
- &VariableSize,
- SystemConfiguration);
- if (VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
- DEBUG ((EFI_D_ERROR, "Setup variable is currputed\n"));
- Status = EFI_BAD_BUFFER_SIZE;
- }
- DEBUG ((EFI_D_INFO, "GetSetupVariable() Exit \n"));
- return Status;
-}
-
-/**
- This is the entry point of PEIM
-
- @param[in] FileHandle Handle of the file being invoked.
- @param[in] PeiServices Describes the list of possible PEI Services.
-
- @retval EFI_SUCCESS If it is completed successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-PeiInitPlatform (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status = EFI_SUCCESS;
- UINTN Size;
- SYSTEM_CONFIGURATION SystemConfiguration;
-
- //
- // Get setup variable. This can only be done after BootMode is updated
- //
- Status = GetSetupVariable (PeiServices, &SystemConfiguration);
- Size = sizeof(SYSTEM_CONFIGURATION);
-
- if(EFI_ERROR(Status)){
- //
- // For OC solution, there is no setup variable, so set the SystemConfiguration with default value.
- //
- CopyMem(&SystemConfiguration, &gDefaultSystemConfiguration,Size);
- //
- // Update the values according to PCD settings
- //
-
- //
- // Platform
- //
- SystemConfiguration.TurboModeEnable = PcdGet8(PcdTurboMode);
-
- //
- // South Complex
- //
- SystemConfiguration.SccSdcardEnabled = PcdGet8(PcdSdcardMode);
- SystemConfiguration.LpssHsuart0Enabled = PcdGet8(PcdEnableHsuart0);
- SystemConfiguration.LpssHsuart1Enabled = PcdGet8(PcdEnableHsuart1);
- SystemConfiguration.PchAzalia = PcdGet8(PcdEnableAzalia);
- SystemConfiguration.PchSata = PcdGet8(PcdEnableSata);
- SystemConfiguration.PchUsb30Mode = PcdGet8(PcdEnableXhci);
- SystemConfiguration.PchLpeEnabled = PcdGet8(PcdEnableLpe);
- SystemConfiguration.LpssDma0Enabled = PcdGet8(PcdEnableDma0);
- SystemConfiguration.LpssDma1Enabled = PcdGet8(PcdEnableDma1);
- SystemConfiguration.LpssI2C0Enabled = PcdGet8(PcdEnableI2C0);
- SystemConfiguration.LpssI2C1Enabled = PcdGet8(PcdEnableI2C1);
- SystemConfiguration.LpssI2C2Enabled = PcdGet8(PcdEnableI2C2);
- SystemConfiguration.LpssI2C3Enabled = PcdGet8(PcdEnableI2C3);
- SystemConfiguration.LpssI2C4Enabled = PcdGet8(PcdEnableI2C4);
- SystemConfiguration.LpssI2C5Enabled = PcdGet8(PcdEnableI2C5);
- SystemConfiguration.LpssI2C6Enabled = PcdGet8(PcdEnableI2C6);
- SystemConfiguration.ScceMMCEnabled = PcdGet8(PcdEmmcMode);
- SystemConfiguration.SataInterfaceSpeed = PcdGet8(PcdSataInterfaceSpeed);
- SystemConfiguration.ISPEn = PcdGet8(ISPEnable);
- SystemConfiguration.ISPDevSel = PcdGet8(ISPPciDevConfig);
- SystemConfiguration.PchSata = PcdGet8(PcdEnableSata);
- SystemConfiguration.MrcDvfsEnable = PcdGet8(PcdDvfsEnable);
- SystemConfiguration.PnpSettings = PcdGet8(PcdPnpSettings);
-
- //
- // North Complex
- //
- SystemConfiguration.GTTSize = PcdGet8(PcdGttSize);
- SystemConfiguration.IgdApertureSize = PcdGet8(PcdApertureSize);
- SystemConfiguration.IgdDvmt50PreAlloc = PcdGet8(PcdIgdDvmt50PreAlloc);
- SystemConfiguration.TSEGSizeSel = (UINT8)PcdGet16(PcdMrcInitTsegSize);
- DEBUG ((EFI_D_INFO, "PeiInitPlatform(): GetSetupVariable returns EFI_NOT_FOUND!! \n"));
- }else {
- // Chipsec: Go thrugh all setup items is corrupted one by one
- CheckSetupVarItem(&SystemConfiguration);
- }
- PcdSetPtr (PcdSystemConfiguration, &Size, &SystemConfiguration);
- DEBUG ((EFI_D_INFO, "PcdSystemConfiguration size - 0x%x\n", LibPcdGetExSize(&gEfiEdkIIPlatformTokenSpaceGuid, PcdTokenEx(&gEfiEdkIIPlatformTokenSpaceGuid, PcdSystemConfiguration)) ));
-
- //
- // Initialize Stall PPIs
- //
- Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi[0]);
- ASSERT_EFI_ERROR (Status);
-
- Status = (*PeiServices)->NotifyPpi (PeiServices, &mMemoryDiscoveredNotifyList[0]);
- ASSERT_EFI_ERROR (Status);
- Status = (*PeiServices)->NotifyPpi (PeiServices, &mEndOfPeiNotifyList[0]);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Start board detection
- //
- Status = PeiServicesInstallPpi (mBoardDetectionStartPpi);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Set the new boot mode for MRC
- //
- Status = UpdateBootMode (PeiServices);
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PlatformHookPoints.c b/BraswellPlatformPkg/Common/PlatformPei/PlatformHookPoints.c new file mode 100644 index 0000000000..1bb85fd614 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PlatformHookPoints.c @@ -0,0 +1,74 @@ +/** @file
+ This PEIM provides several hook points for initializing platform at different POST stage.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformPei.h"
+#include "PlatformBaseAddresses.h"
+#include "PchRegs.h"
+#include <Guid/PlatformInfo.h>
+#include "ChvAccess.h"
+#include <Library/GpioLib.h>
+#include <Guid/Chv2Variable.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Ppi/BoardDetection.h>
+#include <Guid/SetupVariable.h>
+
+EFI_STATUS
+EFIAPI
+PreMemoryInitialization(
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ //
+ // Add code here for pre-memory initialization.
+ //
+
+
+ return EFI_SUCCESS;
+}
+
+
+
+
+EFI_STATUS
+EFIAPI
+PostMemoryInitialization(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ //
+ // Add code here for platform initialization after DRAM initialization but before chipset initialization.
+ //
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PostSiliconInitialization(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ //
+ // Add code here for platform initialization after all silicon initialization (FSP APIs) have been done.
+ //
+
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.c b/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.c new file mode 100644 index 0000000000..5c7b7065a9 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.c @@ -0,0 +1,139 @@ +/** @file
+ This PEIM initialize platform for MRC, following action is performed,
+ 1. Initialize GMCH
+ 2. Detect boot mode
+ 3. Detect video adapter to determine whether we need pre-allocated memory
+ 4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.
+ This file contains the main entry point of the PEIM.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformPei.h"
+#include "PlatformBaseAddresses.h"
+#include "PchRegs.h"
+#include <Guid/PlatformInfo.h>
+#include "ChvAccess.h"
+#include <Library/GpioLib.h>
+#include <Guid/Chv2Variable.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Ppi/BoardDetection.h>
+#include <Guid/SetupVariable.h>
+
+
+//
+// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory
+//
+
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ );
+
+static EFI_PEI_STALL_PPI mStallPpi = {
+ PEI_STALL_RESOLUTION,
+ Stall
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPeiStallPpiGuid,
+ &mStallPpi
+ }
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mBoardDetectionStartPpi[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBoardDetectionStartPpiGuid,
+ NULL
+ }
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ MemoryDiscoveredPpiNotifyCallback
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ PostMemoryInitialization
+ }
+};
+
+EFI_PEI_NOTIFY_DESCRIPTOR mFspInitDoneNotifyList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gFspInitDonePpiGuid,
+ PostSiliconInitialization
+ }
+};
+
+EFI_STATUS
+PeiInitPlatform (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Init PcdSystemConfiguration.
+ //
+ Status = GetSystemConfiguration(PeiServices);
+
+ //
+ // Initialize Stall PPIs.
+ //
+ Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Start board detection.
+ //
+ Status = PeiServicesInstallPpi (mBoardDetectionStartPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set the new boot mode for MRC.
+ //
+ Status = UpdateBootMode (PeiServices);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Add code here for pre-memory initialization.
+ //
+ Status =PreMemoryInitialization (PeiServices);
+
+ //
+ // Register callback functions to gEfiPeiMemoryDiscoveredPpiGuid, which will be triggered when
+ // after DRAM initialization but before chipset initialization.
+ //
+ Status = (*PeiServices)->NotifyPpi (PeiServices, &mMemoryDiscoveredNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register callback functions to gFspInitDonePpiGuid, which will be triggered when
+ // all silicon initialzations have been done by FSP.
+ //
+ Status = (*PeiServices)->NotifyPpi (PeiServices, &mFspInitDoneNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/Platform.h b/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.h index af6a2eb8f9..53ab67a928 100644 --- a/BraswellPlatformPkg/Common/PlatformPei/Platform.h +++ b/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.h @@ -16,6 +16,50 @@ #ifndef __PEI_PLATFORM_H__
#define __PEI_PLATFORM_H__
+#include <FrameworkPei.h>
+#include <IndustryStandard/SmBus.h>
+#include <IndustryStandard/Pci22.h>
+#include <Ppi/AtaController.h>
+#include <Guid/Capsule.h>
+#include <Ppi/Cache.h>
+#include <Ppi/MasterBootMode.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/RecoveryDevice.h>
+#include <Guid/SetupVariable.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/FvLoadFile.h>
+#include <Ppi/DeviceRecoveryModule.h>
+#include <Ppi/Capsule.h>
+#include <Ppi/Reset.h>
+#include <Ppi/Stall.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/Smbus2.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/DebugLib.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/PciCf8Lib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PrintLib.h>
+#include <Library/ResetSystemLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/CacheMaintenanceLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/RecoveryOemHookLib.h>
+
#define PEI_STALL_RESOLUTION 1
#define STALL_PEIM_SIGNATURE SIGNATURE_32('p','p','u','s')
@@ -77,6 +121,29 @@ MemoryDiscoveredPpiNotifyCallback ( IN VOID *Ppi
);
+EFI_STATUS
+EFIAPI
+PostSiliconInitialization(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PostMemoryInitialization(
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PreMemoryInitialization(
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+
/**
This is the callback function notified by FvFileLoader PPI, it depends on FvFileLoader PPI to load
the PEIM into memory.
@@ -89,12 +156,6 @@ MemoryDiscoveredPpiNotifyCallback ( **/
EFI_STATUS
-EndOfPeiPpiNotifyCallback (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
- IN VOID *Ppi
- );
-EFI_STATUS
EFIAPI
FvFileLoaderPpiNotifyCallback (
IN EFI_PEI_SERVICES **PeiServices,
@@ -162,4 +223,11 @@ CapsulePpiNotifyCallback ( IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
);
+
+EFI_STATUS
+GetSystemConfiguration (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
#endif
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.inf b/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.inf index 56eddff260..ff20f8d34a 100644 --- a/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.inf +++ b/BraswellPlatformPkg/Common/PlatformPei/PlatformPei.inf @@ -4,7 +4,7 @@ # This module will do chipset programming, create platforminfo hob, install
# required mmio policy ppi.
#
-# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -23,16 +23,19 @@ MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = PeiInitPlatform
- PI_SPECIFICATION_VERSION = 0x0001000A
+ PI_SPECIFICATION_VERSION = 0x0001000A
[Sources.common]
- Generic/Recovery.c
- Platform.c
- Platform.h
- MemoryCallback.c
- CommonHeader.h
- Stall.c
- BootMode.c
+ PreMemory/Stall.c
+ PreMemory/BootMode.c
+ PreMemory/SystemConfiguration.c
+ PostMemory/MemoryCallback.c
+ PostMemory/Recovery.c
+ PlatformPei.c
+ PlatformPei.h
+ PlatformHookPoints.c
+
+
[Packages]
MdePkg/MdePkg.dec
@@ -44,6 +47,7 @@ UefiCpuPkg/UefiCpuPkg.dec
CryptoPkg/CryptoPkg.dec
ChvFspBinPkg/ChvFspBinPkg.dec
+ IntelFspWrapperPkg/IntelFspWrapperPkg.dec
[LibraryClasses]
PeimEntryPoint
@@ -75,10 +79,12 @@ ## PRODUCES
gEfiPeiMasterBootModePpiGuid
+ ## PRODUCES
gBoardDetectionStartPpiGuid
- ## NOTIFY
- gEfiEndOfPeiSignalPpiGuid
+ ## CONSUMES
+ gFspInitDonePpiGuid
+
[Guids]
## SOMETIMES_CONSUMES ## Variable:L"Setup"
gEfiSetupVariableGuid
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostMemory/MemoryCallback.c b/BraswellPlatformPkg/Common/PlatformPei/PostMemory/MemoryCallback.c new file mode 100644 index 0000000000..6d1af2ead7 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostMemory/MemoryCallback.c @@ -0,0 +1,115 @@ +/** @file
+ This file includes a memory call back function notified when MRC is done,
+ following action is performed in this file,
+ 1. ICH initialization after MRC.
+ 2. SIO initialization.
+ 3. Install ResetSystem and FinvFv PPI.
+ 4. Set MTRR for PEI
+ 5. Create FV HOB and Flash HOB
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformPei.h"
+#include <Ppi/Cache.h>
+#include <Library/BaseCryptLib.h>
+#include <Guid/PlatformInfo.h>
+#include "ChvAccess.h"
+
+/**
+ This function will be called when MRC is done.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Information about the notify event..
+ @param[in] Ppi The notify context.
+
+ @retval EFI_SUCCESS If the function completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT32 Pages;
+ VOID* Memory;
+ UINTN Size;
+
+ Status = (*PeiServices)->GetBootMode (
+ (const EFI_PEI_SERVICES **)PeiServices,
+ &BootMode
+ );
+
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ //
+ // Install Recovery PPI
+ //
+ Status = InitializeRecovery ((EFI_PEI_SERVICES **)PeiServices);
+ ASSERT_EFI_ERROR (Status);
+
+ }
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ Size = PcdGet32(PcdFlashFvRecovery2Size);
+ if (Size > 0) {
+ Pages= (Size + 0xFFF)/0x1000;
+
+ Memory = AllocatePages ( Pages );
+ CopyMem(Memory , (VOID *) PcdGet32(PcdFlashFvRecovery2Base) , Size);
+
+ //
+ // We don't verify just load
+ //
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) Memory,
+ PcdGet32 (PcdFlashFvRecovery2Size),
+ NULL,
+ NULL
+ );
+ }
+
+ if (BootMode != BOOT_IN_RECOVERY_MODE){
+ Size = PcdGet32(PcdFlashFvMainSize);
+ Pages= (Size + 0xFFF)/0x1000;
+
+ Memory = AllocatePages (Pages);
+ CopyMem(Memory , (VOID *) PcdGet32(PcdFlashFvMainBase) , Size);
+
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) Memory,
+ PcdGet32 (PcdFlashFvMainSize),
+ NULL,
+ NULL
+ );
+ }
+ }
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ PeiServicesInstallFvInfoPpi (
+ NULL,
+ (VOID *) (UINTN) (PcdGet32 (PcdFlashFvRecovery2Base)),
+ PcdGet32 (PcdFlashFvRecovery2Size),
+ NULL,
+ NULL
+ );
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/Generic/Recovery.c b/BraswellPlatformPkg/Common/PlatformPei/PostMemory/Recovery.c index 4813a77587..e2d1e91a46 100644 --- a/BraswellPlatformPkg/Common/PlatformPei/Generic/Recovery.c +++ b/BraswellPlatformPkg/Common/PlatformPei/PostMemory/Recovery.c @@ -32,7 +32,7 @@ **/
-#include "CommonHeader.h"
+#include "PlatformPei.h"
EFI_STATUS
EFIAPI
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/MemoryCallback.c b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/MemoryCallback.c new file mode 100644 index 0000000000..f42acc2a21 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/MemoryCallback.c @@ -0,0 +1,299 @@ +/** @file
+ EFI 2.0 PEIM termination callback to provide the platform.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformEarlyInit.h"
+
+VOID
+UpdateDefaultSetupValue (
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfo
+ )
+{
+return;
+}
+
+/**
+ PEI termination callback.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Not uesed.
+ @param[in] Ppi Not uesed.
+
+ @retval EFI_SUCCESS If the interface could be successfully
+ installed.
+
+**/
+EFI_STATUS
+EndOfPeiPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ UINT64 MemoryTop;
+ UINT64 LowUncableBase;
+ EFI_PLATFORM_INFO_HOB *PlatformInfo;
+ UINT32 HecBaseHigh;
+ EFI_BOOT_MODE BootMode;
+
+ Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Set the some PCI and chipset range as UC
+ // And align to 1M at leaset
+ //
+ PlatformInfo = PcdGetPtr (PcdPlatformInfo);
+
+ UpdateDefaultSetupValue (PlatformInfo);
+
+ DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));
+ DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));
+ DEBUG (
+ (EFI_D_ERROR,
+ "PCIE BASE: %lX Size : %X\n",
+ PlatformInfo->PciData.PciExpressBase,
+ PlatformInfo->PciData.PciExpressSize)
+ );
+ DEBUG (
+ (EFI_D_ERROR,
+ "PCI32 BASE: %X Limit: %X\n",
+ PlatformInfo->PciData.PciResourceMem32Base,
+ PlatformInfo->PciData.PciResourceMem32Limit)
+ );
+ DEBUG (
+ (EFI_D_ERROR,
+ "PCI64 BASE: %lX Limit: %lX\n",
+ PlatformInfo->PciData.PciResourceMem64Base,
+ PlatformInfo->PciData.PciResourceMem64Limit)
+ );
+ DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));
+
+ LowUncableBase = PlatformInfo->MemData.MemMaxTolm;
+ LowUncableBase &= (0x0FFF00000);
+ MemoryTop = (0x100000000);
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ //
+ // In BIOS, HECBASE will be always below 4GB
+ //
+ HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);
+ ASSERT (HecBaseHigh < 16);
+
+ //
+ // Programe HECBASE for DXE phase
+ //
+ }
+
+ return Status;
+}
+
+/**
+ Install Firmware Volume Hob's once there is main memory
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Notify that this module published.
+ @param[in] Ppi PPI that was installed.
+
+ @retval EFI_SUCCESS The function completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_CPUID_REGISTER FeatureInfo;
+ UINT8 CpuAddressWidth;
+ UINT32 RootComplexBar;
+ UINT32 PmcBase;
+ UINT32 IoBase;
+ UINT32 IlbBase;
+ UINT32 SpiBase;
+ UINT32 MphyBase;
+ UINT32 PunitBase;
+
+ //
+ // Pulish memory type info
+ //
+ PublishMemoryTypeInfo ();
+
+ RootComplexBar = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA) & B_PCH_LPC_RCBA_BAR;
+ DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));
+ ASSERT (RootComplexBar != 0 && RootComplexBar != B_PCH_LPC_RCBA_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ RootComplexBar,
+ 0x1000
+ );
+
+ PmcBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR;
+ DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));
+ ASSERT (PmcBase != 0 && PmcBase != B_PCH_LPC_PMC_BASE_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ PmcBase,
+ 0x1000
+ );
+
+ IoBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;
+ DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));
+ ASSERT (IoBase != 0 && IoBase != B_PCH_LPC_IO_BASE_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ IoBase,
+ 0x40000
+ );
+
+ IlbBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE) & B_PCH_LPC_ILB_BASE_BAR;
+ DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));
+ ASSERT (IlbBase != 0 && IlbBase != B_PCH_LPC_ILB_BASE_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ IlbBase,
+ 0x2000
+ );
+
+ SpiBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
+ DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));
+ ASSERT (SpiBase != 0 && SpiBase != B_PCH_LPC_SPI_BASE_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ SpiBase,
+ 0x1000
+ );
+
+ MphyBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE) & B_PCH_LPC_MPHY_BASE_BAR;
+ DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));
+ ASSERT (MphyBase != 0 && MphyBase != B_PCH_LPC_MPHY_BASE_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ MphyBase,
+ 0x100000
+ );
+
+ PunitBase = MmPci32 (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PUNIT_BASE) & B_PCH_LPC_PUNIT_BASE_BAR;
+ DEBUG ((EFI_D_INFO, "PunitBase : 0x%x\n", PunitBase));
+ ASSERT (PunitBase != 0 && PunitBase != B_PCH_LPC_PUNIT_BASE_BAR);
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ PunitBase,
+ 0x1000
+ );
+ //
+ // Local APIC
+ //
+ DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ LOCAL_APIC_ADDRESS,
+ 0x1000
+ );
+ //
+ // IO APIC
+ //
+ DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS));
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ IO_APIC_ADDRESS,
+ 0x1000
+ );
+ //
+ // Adding the PCIE Express area to the E820 memory table as type 2 memory.
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ ((UINTN)PcdGet64(PcdPciExpressBaseAddress)), //PlatformInfo->PciData.PciExpressBase,
+ 0x10000000 //PlatformInfo->PciData.PciExpressSize
+ );
+ //
+ // Adding the Flashpart to the E820 memory table as type 2 memory.
+ //
+ DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", PcdGet32(PcdFlashAreaBaseAddress)));
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_FIRMWARE_DEVICE,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ PcdGet32(PcdFlashAreaBaseAddress),
+ PcdGet32(PcdFlashAreaSize)
+ );
+
+ //
+ // Create a CPU hand-off information
+ //
+ CpuAddressWidth = 32;
+ AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
+ if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {
+ AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);
+ CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
+ }
+
+ BuildCpuHob(CpuAddressWidth, 16);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+ValidateFvHeader (
+ IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader
+ )
+{
+ UINT16 *Ptr;
+ UINT16 HeaderLength;
+ UINT16 Checksum;
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
+ (FwVolHeader->FvLength == ((UINT64) -1)) ||
+ ((FwVolHeader->HeaderLength & 0x01) != 0)
+ ) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Verify the header checksum
+ //
+ HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);
+ Ptr = (UINT16 *) FwVolHeader;
+ Checksum = 0;
+ while (HeaderLength > 0) {
+ Checksum = *Ptr++;
+ HeaderLength--;
+ }
+
+ if (Checksum != 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/MemoryPeim.c b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/MemoryPeim.c new file mode 100644 index 0000000000..58445cd717 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/MemoryPeim.c @@ -0,0 +1,110 @@ +/** @file
+ Tiano PEIM to provide the platform support functionality.
+ This file implements the Platform Memory Range PPI.
+
+ Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformEarlyInit.h"
+
+//
+// Need min. of 48MB PEI phase
+//
+#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)
+
+//
+// This is the memory needed for PEI to start up DXE.
+//
+// Over-estimating this size will lead to higher fragmentation
+// of main memory. Under-estimation of this will cause catastrophic
+// failure of PEI to load DXE. Generally, the failure may only be
+// realized during capsule updates.
+//
+#define PRERESERVED_PEI_MEMORY ( \
+ EFI_SIZE_TO_PAGES (3 * 0x800000) /* PEI Core memory based stack */ \
+ )
+
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIReclaimMemory, 0x2B }, // ASL
+ { EfiACPIMemoryNVS, 0xCF }, // ACPI NVS
+ { EfiReservedMemoryType, 0xC8 }, // BIOS Reserved
+ { EfiRuntimeServicesCode, 0x100 },
+ { EfiRuntimeServicesData, 0x200 },
+ { EfiMaxMemoryType, 0 }
+};
+
+/**
+ Publish Memory Type Information.
+
+ @param None
+
+ @retval EFI_SUCCESS Success.
+ @retval Others Errors have occurred.
+**/
+EFI_STATUS
+EFIAPI
+PublishMemoryTypeInfo (
+ void
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
+
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ &Variable
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "WARNING: Locating Pei variable failed 0x%x \n", Status));
+ DEBUG((EFI_D_ERROR, "Build Hob from default\n"));
+ //
+ // Build the default GUID'd HOB for DXE
+ //
+ BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, mDefaultMemoryTypeInformation, sizeof (mDefaultMemoryTypeInformation) );
+
+ return Status;
+ }
+
+ DataSize = sizeof (MemoryData);
+ //
+ // This variable is saved in BDS stage. Now read it back
+ //
+ Status = Variable->GetVariable (
+ Variable,
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+ &gEfiMemoryTypeInformationGuid,
+ NULL,
+ &DataSize,
+ &MemoryData
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // build default
+ //
+ DEBUG((EFI_D_ERROR, "Build Hob from default\n"));
+ BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, mDefaultMemoryTypeInformation, sizeof (mDefaultMemoryTypeInformation) );
+ } else {
+ //
+ // Build the GUID'd HOB for DXE from variable
+ //
+ DEBUG((EFI_D_ERROR, "Build Hob from variable \n"));
+ BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, MemoryData, DataSize);
+ }
+
+ return Status;
+}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformEarlyInit.c b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformEarlyInit.c new file mode 100644 index 0000000000..5c2381cb4c --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformEarlyInit.c @@ -0,0 +1,207 @@ +/** @file
+ Do platform specific PEI stage initializations.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformEarlyInit.h"
+#include <Library/BiosIdLib.h>
+#include <CpuRegs.h>
+#include <CpuPpmLib.h>
+
+#pragma optimize ("", off)
+
+static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {
+ FindFv
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiFindFvPpiGuid,
+ &mEfiFindFvPpi
+ }
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
+ &gEfiEndOfPeiSignalPpiGuid,
+ EndOfPeiPpiNotifyCallback
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ MemoryDiscoveredPpiNotifyCallback
+ }
+};
+
+
+/**
+ Bugbug: temp workaround - Initialize performance to HFM.
+
+ @param[in] None
+
+**/
+VOID
+ProcessorsPerfPowerInit (
+ )
+{
+ EFI_CPUID_REGISTER Cpuid = { 0, 0, 0, 0 };
+ UINT16 MaxBusRatio;
+ UINT16 MaxVid;
+ MSR_REGISTER Ia32MiscEnable;
+ MSR_REGISTER TempMsr;
+ MSR_REGISTER IaCoreRatios;
+ MSR_REGISTER IaCoreVids;
+
+
+ //
+ // Get Maximum Non-Turbo bus ratio (HFM) from IACORE_RATIOS MSR Bits[23:16]
+ //
+ IaCoreRatios.Qword = AsmReadMsr64 (MSR_IACORE_RATIOS);
+ MaxBusRatio = IaCoreRatios.Bytes.ThirdByte;
+
+ //
+ // Get Maximum Non-Turbo Vid (HFM) from IACORE_VIDS MSR Bits[23:16]
+ //
+ IaCoreVids.Qword = AsmReadMsr64 (MSR_IACORE_VIDS);
+ MaxVid = IaCoreVids.Bytes.ThirdByte;
+
+ AsmCpuid (EFI_CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+
+ //
+ // This function will be executed when EIST is enabled and EIST is capable
+ // So processor can be switched to HFM
+ //
+ if ((Cpuid.RegEcx & B_EFI_CPUID_VERSION_INFO_ECX_EIST) == B_EFI_CPUID_VERSION_INFO_ECX_EIST) {
+
+ //
+ // Enable EIST
+ //
+ Ia32MiscEnable.Qword = AsmReadMsr64 (EFI_MSR_IA32_MISC_ENABLE);
+ Ia32MiscEnable.Qword |= B_EFI_MSR_IA32_MISC_ENABLE_EIST;
+ AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Ia32MiscEnable.Qword);
+
+ TempMsr.Qword = AsmReadMsr64 (EFI_MSR_IA32_PERF_CTRL);
+ TempMsr.Qword &= (~(UINT64)P_STATE_TARGET_MASK);
+
+ TempMsr.Qword |= LShiftU64 (MaxBusRatio, P_STATE_TARGET_OFFSET);
+ TempMsr.Qword |= (UINT64)MaxVid;
+
+ AsmWriteMsr64 (EFI_MSR_IA32_PERF_CTRL, TempMsr.Qword);
+ }
+
+ return;
+}
+
+/**
+ Platform specific initializations in stage1.
+
+ @param[in] FileHandle Pointer to the PEIM FFS file header.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS Operation completed successfully.
+ @retval Otherwise Platform initialization failed.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformEarlyInitEntry (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+ EFI_PLATFORM_INFO_HOB *PlatformInfo;
+
+ //
+ // Set the some PCI and chipset range as UC
+ // And align to 1M at least
+ //
+ PlatformInfo = PcdGetPtr (PcdPlatformInfo);
+
+ //
+ // Initialize PlatformInfo HOB
+ //
+ MultiPlatformInfoInit (PeiServices, PlatformInfo);
+
+ //
+ // Get setup variable. This can only be done after BootMode is updated
+ //
+ CopyMem (&SystemConfiguration, PcdGetPtr (PcdSystemConfiguration), sizeof(SYSTEM_CONFIGURATION));
+
+ //
+ // Do basic PCH init
+ //
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_COMPUTING_UNIT_CHIPSET | EFI_CHIPSET_PC_PEI_CAR_SB_INIT));
+ Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize platform PPIs
+ //
+ Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Bugbug: temp workaround to increase performance.
+ //
+ ProcessorsPerfPowerInit();
+
+ return Status;
+}
+
+/**
+ Return the mainblockcompact Fv.
+
+ @param[in] This EFI PEI FIND FV PPI instance
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] FvNumber enumeration of the firmware volumes we care about.
+ @param[in] FvAddress Base Address of the memory containing the firmware volume
+
+ @retval EFI_SUCCESS
+ @retval EFI_NOT_FOUND
+
+**/
+EFI_STATUS
+EFIAPI
+FindFv (
+ IN EFI_PEI_FIND_FV_PPI *This,
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT8 *FvNumber,
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress
+ )
+{
+ //
+ // At present, we only have one Fv to search
+ //
+ if (*FvNumber == 0) {
+ *FvNumber = 1;
+ *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) MAINBLOCK_BASE_ADDR;
+ return EFI_SUCCESS;
+ } else if (*FvNumber == 1) {
+ *FvNumber = 2;
+ if (IsA16Inverted ()) {
+ *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BOOTBLOCK2_BACKUP_BASE_ADDR;
+ } else {
+ *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BOOTBLOCK2_BASE_ADDR;
+ }
+ return EFI_SUCCESS;
+ } else { // Not the one Fv we care about
+ return EFI_NOT_FOUND;
+ }
+}
+
+#pragma optimize ("", on)
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformEarlyInit.h b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformEarlyInit.h new file mode 100644 index 0000000000..211b279764 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformEarlyInit.h @@ -0,0 +1,336 @@ +/** @file
+ Platform Early Stage header file
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_PLATFORM_EARLY_INIT_H_
+#define _EFI_PLATFORM_EARLY_INIT_H_
+
+#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x
+
+#include <FrameworkPei.h>
+#include "PlatformBaseAddresses.h"
+#include "PchAccess.h"
+#include "ChvAccess.h"
+#include "CpuRegs.h"
+#include "Platform.h"
+#include "CpuRegs.h"
+#include <Ppi/Stall.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/GpioLib.h>
+#include <Guid/SetupVariable.h>
+#include <Ppi/AtaController.h>
+#include <Ppi/FindFv.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/Capsule.h>
+#include <Library/DebugLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PeiServicesLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Guid/FirmwareFileSystem.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/Cache.h>
+#include <Library/PchPlatformLib.h>
+#include <Ppi/SmbusPolicy.h>
+#include <Ppi/Reset.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Guid/GlobalVariable.h>
+#include <Ppi/RecoveryModule.h>
+#include <Ppi/DeviceRecoveryModulePei.h>
+#include <Guid/Capsule.h>
+#include <Guid/RecoveryDevice.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/I2CLib.h>
+#include <Library/TimerLib.h>
+
+#define SMC_LAN_ON 0x46
+#define SMC_LAN_OFF 0x47
+#define SMC_DEEP_S3_STS 0xB2
+#define EXT_MODEL_ID_VLV2 0x3
+
+typedef struct {
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+} EFI_CPUID_REGISTER;
+
+//
+// Wake Event Types
+//
+#define SMBIOS_WAKEUP_TYPE_RESERVED 0x00
+#define SMBIOS_WAKEUP_TYPE_OTHERS 0x01
+#define SMBIOS_WAKEUP_TYPE_UNKNOWN 0x02
+#define SMBIOS_WAKEUP_TYPE_APM_TIMER 0x03
+#define SMBIOS_WAKEUP_TYPE_MODEM_RING 0x04
+#define SMBIOS_WAKEUP_TYPE_LAN_REMOTE 0x05
+#define SMBIOS_WAKEUP_TYPE_POWER_SWITCH 0x06
+#define SMBIOS_WAKEUP_TYPE_PCI_PME 0x07
+#define SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED 0x08
+
+//
+// Defines for stall ppi
+//
+#define PEI_STALL_RESOLUTION 1
+
+//
+// Used in PEI memory test routines
+//
+#define MEMORY_TEST_COVER_SPAN 0x40000
+#define MEMORY_TEST_PATTERN 0x5A5A5A5A
+
+#define EFI_LOW_BEEP_FREQUENCY 0x31B
+#define EFI_HIGH_BEEP_FREQUENCY 0x254
+
+//
+// General Purpose Constants
+//
+#define ICH_ACPI_TIMER_MAX_VALUE 0x1000000 //The timer is 24 bit overflow
+
+//
+// Function Prototypes
+//
+EFI_STATUS
+PlatformPchInit (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration,
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT16 PlatformType
+ );
+
+EFI_STATUS
+PeimInitializeFlashMap (
+ IN EFI_FFS_FILE_HEADER *FfsHeader,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+PeimInstallFlashMapPpi (
+ IN EFI_FFS_FILE_HEADER *FfsHeader,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+EFIAPI
+IchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+BOOLEAN
+GetSleepTypeAfterWakeup (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT UINT16 *SleepType
+ );
+
+EFI_STATUS
+EFIAPI
+GetWakeupEventAndSaveToHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PeiGetVariable (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CHAR16 *VariableName,
+ IN EFI_GUID * VendorGuid,
+ OUT UINT32 *Attributes OPTIONAL,
+ IN OUT UINTN *DataSize,
+ OUT VOID *Data
+ );
+
+EFI_STATUS
+EFIAPI
+PeiGetNextVariableName (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINTN *VariableNameSize,
+ IN OUT CHAR16 *VariableName,
+ IN OUT EFI_GUID *VendorGuid
+ );
+
+EFI_STATUS
+UpdateBootMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+EndOfPeiPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PeimInitializeRecovery (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+VOID
+CheckPowerOffNow (
+ VOID
+ );
+
+VOID
+IchGpioInit (
+ IN UINT16 PlatformType,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+EFI_STATUS
+PcieSecondaryBusReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun
+ );
+
+VOID
+SetPlatformBootMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+BOOLEAN
+CheckIfJumperSetForRecovery (
+ VOID
+ );
+
+EFI_STATUS
+FindFv (
+ IN EFI_PEI_FIND_FV_PPI *This,
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT8 *FvNumber,
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FVAddress
+ );
+
+BOOLEAN
+IsA16Inverted (
+ );
+
+EFI_STATUS
+EFIAPI
+CpuOnlyReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+EFIAPI
+InitLan (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN SYSTEM_CONFIGURATION *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+Stall (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN CONST EFI_PEI_STALL_PPI *This,
+ IN UINTN Microseconds
+ );
+
+EFI_STATUS
+MultiPlatformInfoInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+BOOLEAN
+IsRecoveryJumper (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
+ );
+
+EFI_STATUS
+PlatformInfoUpdate (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+VOID
+PlatformSaInit (
+IN SYSTEM_CONFIGURATION *SystemConfiguration,
+IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+InitializePlatform (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+EFI_STATUS
+EFIAPI
+SetPeiCacheMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+EFIAPI
+SetDxeCacheMode (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+GPIO_initialization (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *SmbusPpi
+ );
+
+EFI_STATUS
+GeneralPowerFailureHandler (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+BOOLEAN
+IsRtcUipAlwaysSet (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+RtcPowerFailureHandler (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+InitPchUsb (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+EFIAPI
+PublishMemoryTypeInfo (
+ void
+ );
+
+#endif
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformPchInitPeim.c b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformPchInitPeim.c new file mode 100644 index 0000000000..141a8e5db2 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PlatformPchInitPeim.c @@ -0,0 +1,564 @@ +/** @file
+ Do Early PCH platform initialization.
+
+ Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformEarlyInit.h"
+#include <Ppi/PchPlatformPolicy.h>
+#include "PchRegs.h"
+#include "Ppi/PchInit.h"
+#include <Library/PcdLib.h>
+
+
+#define MC_PMSTS_OFFSET 0xC
+
+#define DEFAULT_BUS_INFO 0x2020
+
+VOID
+PchInitInterrupt (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ );
+
+#pragma warning (push)
+#pragma warning (disable : 4245)
+#pragma warning (pop)
+
+UINT8
+ReadCmosBank1Byte (
+ IN UINT8 Address
+ )
+{
+ UINT8 Data;
+
+ IoWrite8 (R_PCH_RTC_EXT_INDEX, Address);
+ Data = IoRead8 (R_PCH_RTC_EXT_TARGET);
+
+ return Data;
+}
+
+VOID
+WriteCmosBank1Byte (
+ IN UINT8 Address,
+ IN UINT8 Data
+ )
+{
+ IoWrite8 (R_PCH_RTC_EXT_INDEX, Address);
+ IoWrite8 (R_PCH_RTC_EXT_TARGET, Data);
+}
+
+/**
+ Turn off system if needed.
+
+ @param[in]
+
+ @retval
+
+**/
+VOID
+CheckPowerOffNow (
+ VOID
+ )
+{
+ UINT16 Pm1Sts;
+
+ //
+ // Read and check the ACPI registers
+ //
+ Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
+ if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);
+ }
+}
+
+VOID
+ClearPowerState (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ UINT8 Data8;
+ UINT16 Data16;
+ UINT32 Data32;
+
+ //
+ // Check for PowerState option for AC power loss and program the chipset
+ //
+
+ //
+ // Clear PWROK (Set to Clear)
+ //
+ MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR);
+
+ //
+ // Clear Power Failure Bit (Set to Clear)
+ //
+ // TODO: Check if it is OK to clear here
+ MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);
+
+ //
+ // Clear the GPE and PM enable
+ //
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_EN, (UINT16) 0x00);
+ IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_EN, (UINT32) 0x00);
+
+ //
+ // Halt the TCO timer
+ //
+ Data16 = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT);
+ Data16 |= B_PCH_TCO_CNT_TMR_HLT;
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT, Data16);
+
+ //
+ // if NMI_NOW_STS is set
+ // Write '1' to Invert NMI_NOW & NMI_NOW_STS
+ //
+ Data8 = MmioRead8(ILB_BASE_ADDRESS + R_PCH_ILB_GNMI);
+ if ((Data8 & B_PCH_ILB_GNMI_NMINS) == B_PCH_ILB_GNMI_NMINS) {
+ MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_GNMI, B_PCH_ILB_GNMI_NMIN);
+ }
+ //
+ // Before we clear the TO status bit here we need to save the results in a CMOS bit for later use.
+ //
+ Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);
+ if ((Data32 & B_PCH_TCO_STS_SECOND_TO) == B_PCH_TCO_STS_SECOND_TO) {
+#if (defined(HW_WATCHDOG_TIMER_SUPPORT) && (HW_WATCHDOG_TIMER_SUPPORT != 0))
+ WriteCmosBank1Byte (
+ EFI_CMOS_PERFORMANCE_FLAGS,
+ ReadCmosBank1Byte (EFI_CMOS_PERFORMANCE_FLAGS) | B_CMOS_TCO_WDT_RESET
+ );
+#endif
+ }
+ //
+ // Now clear the TO status bit (Write '1' to clear)
+ //
+ IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS, (UINT32) (Data32 | B_PCH_TCO_STS_SECOND_TO));
+}
+
+/**
+ Clear any SMI status or wake status left over from boot.
+
+ @param[in]
+
+ @retval
+
+**/
+VOID
+ClearSmiAndWake (
+ VOID
+ )
+{
+ UINT16 Pm1Sts;
+ UINT32 Gpe0Sts;
+ UINT32 SmiSts;
+
+ //
+ // Read the ACPI registers
+ //
+ Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
+ Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
+ SmiSts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS);
+
+ //
+ // Clear any SMI or wake state from the boot
+ //
+ Pm1Sts = (B_PCH_ACPI_PM1_STS_PRBTNOR | B_PCH_ACPI_PM1_STS_PWRBTN);
+
+ Gpe0Sts |=
+ (
+ B_PCH_ACPI_GPE0a_STS_CORE_GPIO |
+ B_PCH_ACPI_GPE0a_STS_SUS_GPIO |
+ B_PCH_ACPI_GPE0a_STS_TCO |
+ B_PCH_ACPI_GPE0a_STS_PME_B0 |
+ B_PCH_ACPI_GPE0a_STS_BATLOW |
+ B_PCH_ACPI_GPE0a_STS_PCI_EXP |
+ B_PCH_ACPI_GPE0a_STS_GUNIT_SCI |
+ B_PCH_ACPI_GPE0a_STS_PUNIT_SCI |
+ B_PCH_ACPI_GPE0a_STS_SWGPE |
+ B_PCH_ACPI_GPE0a_STS_HOT_PLUG |
+ B_PCH_ACPI_GPE0a_STS_PMU_WAKEB
+ );
+
+ SmiSts |=
+ (
+ B_PCH_SMI_STS_SMBUS |
+ B_PCH_SMI_STS_PERIODIC |
+ B_PCH_SMI_STS_TCO |
+ B_PCH_SMI_STS_SWSMI_TMR |
+ B_PCH_SMI_STS_APM |
+ B_PCH_SMI_STS_ON_SLP_EN |
+ B_PCH_SMI_STS_BIOS
+ );
+
+ //
+ // Write them back
+ //
+ IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, Pm1Sts);
+ IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS, Gpe0Sts);
+ IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS, SmiSts);
+}
+
+/**
+ Issue PCI-E Secondary Bus Reset
+
+ @param[in] PeiServices General-purpose services that are available to every PEIM.
+ @param[in] Bus Bus number of the bridge
+ @param[in] Dev Devices number of the bridge
+ @param[in] Fun Function number of the bridge
+
+ @retval EFI_SUCCESS
+
+**/
+EFI_STATUS
+PcieSecondaryBusReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT8 Bus,
+ IN UINT8 Dev,
+ IN UINT8 Fun
+ )
+{
+ EFI_PEI_STALL_PPI *PeiStall;
+ EFI_STATUS Status;
+
+ Status = (**PeiServices).LocatePpi (
+ PeiServices,
+ &gEfiPeiStallPpiGuid,
+ 0,
+ NULL,
+ &PeiStall
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Issue secondary bus reset
+ //
+ MmPci16Or(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS);
+
+ //
+ // Wait 1ms
+ //
+ PeiStall->Stall (PeiServices, PeiStall, 1000);
+
+ //
+ // Clear the reset bit
+ // Note: The PCIe spec suggests 100ms delay between clearing this bit and accessing
+ // the device's config space. Since we will not access the config space until we enter DXE
+ // we don't put delay expressly here.
+ //
+ MmPci16And(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, ~(EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Provide hard reset PPI service.
+ To generate full hard reset, write 0x0E to ICH RESET_GENERATOR_PORT (0xCF9).
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval Not return System reset occured.
+ @retval EFI_DEVICE_ERROR Device error, could not reset the system.
+
+**/
+EFI_STATUS
+EFIAPI
+IchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ IoWrite8 (
+ R_PCH_RST_CNT,
+ V_PCH_RST_CNT_HARDSTARTSTATE
+ );
+
+ IoWrite8 (
+ R_PCH_RST_CNT,
+ V_PCH_RST_CNT_HARDRESET
+ );
+
+ //
+ // System reset occured, should never reach at this line.
+ //
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+
+ return EFI_DEVICE_ERROR;
+}
+
+VOID
+PchPlatformLpcInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ EFI_BOOT_MODE BootMode;
+ UINT8 Data8;
+ UINT16 Data16;
+
+ (*PeiServices)->GetBootMode(PeiServices, &BootMode);
+
+ if ((BootMode != BOOT_ON_S3_RESUME)) {
+ //
+ // Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI
+ //
+ ClearSmiAndWake ();
+ }
+
+ ClearPowerState (SystemConfiguration);
+
+ //
+ // Disable SERR NMI and IOCHK# NMI in port 61
+ //
+ Data8 = IoRead8 (R_PCH_NMI_SC);
+ IoWrite8(R_PCH_NMI_SC, (UINT8) (Data8 | B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN));
+
+ //
+ // Enable Bus Master, I/O, Mem, and SERR on LPC bridge
+ //
+ Data16 = PchLpcPciCfg16 (R_PCH_LPC_COMMAND);
+ MmioWrite16 (
+ MmPciAddress (0,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ R_PCH_LPC_COMMAND
+ ),
+ (Data16 |
+ B_PCH_LPC_COMMAND_IOSE |
+ B_PCH_LPC_COMMAND_MSE |
+ B_PCH_LPC_COMMAND_BME |
+ B_PCH_LPC_COMMAND_SERR_EN)
+ );
+}
+
+VOID
+IchRcrbInit (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ EFI_BOOT_MODE BootMode;
+
+ (*PeiServices)->GetBootMode(PeiServices, &BootMode);
+
+ //
+ // If not recovery or flash update boot path. set the BIOS interface lock down bit.
+ // It locks the top swap bit and BIOS boot strap bits from being changed.
+ //
+ if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) {
+ MmioOr8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS, B_PCH_RCRB_GCS_BILD);
+ }
+
+ //
+ // Disable the Watchdog timer expiration from causing a system reset
+ //
+ MmioOr8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, B_PCH_PMC_PM_CFG_NO_REBOOT);
+
+ if ((BootMode == BOOT_ON_S3_RESUME)) {
+ //
+ // We are resuming from S3
+ // Program HPET based on Setup
+ //
+ if (SystemConfiguration->Hpet == 1) {
+ MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG, B_PCH_PCH_HPET_GCFG_EN);
+ } else {
+ MmioAnd8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG, (UINT8) ~(B_PCH_PCH_HPET_GCFG_EN));
+ }
+ }
+}
+
+VOID
+PchInitInterrupt (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ DEBUG ((EFI_D_ERROR, "PchInitInterrupt () - Start\n"));
+
+ //
+ // Configure LPSS Interrupts (Done by FSP)
+ //
+
+ //
+ // Program Interrupt routing registers
+ //
+ //
+ // Device 31 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D31IR),
+ V_PCH_ILB_DXXIR_IBR_PIRQC // For SMBUS
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D31IR); // Read Posted Writes Register
+
+ //
+ // Device 30 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D30IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQD + // For LPSS1
+ V_PCH_ILB_DXXIR_IBR_PIRQB +
+ V_PCH_ILB_DXXIR_ICR_PIRQC +
+ V_PCH_ILB_DXXIR_IDR_PIRQA
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D30IR); // Read Posted Writes Register
+
+ //
+ // Device 28 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D28IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQA + // For PCIe #1
+ V_PCH_ILB_DXXIR_IBR_PIRQB + // For PCIe #2
+ V_PCH_ILB_DXXIR_ICR_PIRQC + // For PCIe #3
+ V_PCH_ILB_DXXIR_IDR_PIRQD // For PCIe #4
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D28IR); // Read Posted Writes Register
+ //
+ // Device 27 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D27IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQG // For Azalia
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D27IR); // Read Posted Writes Register
+
+ //
+ // Device 26 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D26IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQF // For SEC
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D26IR); // Read Posted Writes Register
+
+ //
+ // Device 24 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D24IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQB | // For LPSS2
+ V_PCH_ILB_DXXIR_IBR_PIRQA |
+ V_PCH_ILB_DXXIR_ICR_PIRQD |
+ V_PCH_ILB_DXXIR_IDR_PIRQC
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D24IR); // Read Posted Writes Register
+
+ //
+ // Device 22 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D22IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQH // For OTG
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D22IR); // Read Posted Writes Register
+
+ //
+ // Device 21 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D21IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQF // For LPE
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D21IR); // Read Posted Writes Register
+
+ //
+ // Device 20 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D20IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQE // For xHCI
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D20IR); // Read Posted Writes Register
+ //
+ // Device 19 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D19IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQD // For SATA
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D19IR); // Read Posted Writes Register
+
+ //
+ // Device 18 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D18IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQC // For SDIO #2
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D18IR); // Read Posted Writes Register
+
+ //
+ // Device 17 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D17IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQB // For SDIO #1
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D17IR); // Read Posted Writes Register
+
+ //
+ // Device 16 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D16IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQA // For SDIO #0
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D16IR); // Read Posted Writes Register
+
+ //
+ // Device 10 Interrupt Route
+ //
+ MmioWrite16 (
+ (ILB_BASE_ADDRESS + R_PCH_ILB_D10IR),
+ V_PCH_ILB_DXXIR_IAR_PIRQE // For ISH
+ );
+ MmioRead16 (ILB_BASE_ADDRESS + R_PCH_ILB_D10IR); // Read Posted Writes Register
+
+ DEBUG ((EFI_D_ERROR, "PchInitInterrupt () - End\n"));
+}
+
+EFI_STATUS
+PlatformPchInit (
+ IN SYSTEM_CONFIGURATION *SystemConfiguration,
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN UINT16 PlatformType
+ )
+{
+ //
+ // Setup Interrupt Routing
+ //
+ PchInitInterrupt (SystemConfiguration);
+
+ PchPlatformLpcInit (PeiServices, SystemConfiguration);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the state of A16 inversion
+
+ @param
+
+ @retval TRUE A16 is inverted
+ @retval FALSE A16 is not inverted
+
+**/
+BOOLEAN
+IsA16Inverted (
+ )
+{
+ UINT8 Data;
+
+ Data = MmioRead8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS);
+ return (Data & B_PCH_RCRB_GCS_TS) ? TRUE : FALSE;
+}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PostSiliconInit.inf b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PostSiliconInit.inf new file mode 100644 index 0000000000..08a41e685e --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PostSilicon/PostSiliconInit.inf @@ -0,0 +1,97 @@ +## @file
+# Component description file for PlatformEarlyInit module
+#
+# This module will do early platform initialization during pei stage.
+#
+# Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformEarlyInit
+ FILE_GUID = E039B4AC-DAB5-44FC-AA40-86079CE4C263
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ PI_SPECIFICATION_VERSION = 0x0001000A
+ ENTRY_POINT = PlatformEarlyInitEntry
+
+[Sources.common]
+ PlatformPchInitPeim.c
+ MemoryCallback.c
+ MemoryPeim.c
+ PlatformEarlyInit.c
+ PlatformEarlyInit.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ BraswellPlatformPkg/BraswellPlatformPkg.dec
+ IntelFrameworkPkg/IntelFrameworkPkg.dec
+ ChvRefCodePkg/ChvRefCodePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ HobLib
+ IoLib
+ MultiPlatformLib
+ PcdLib
+ ReportStatusCodeLib
+ PchPlatformLib
+ TimerLib
+
+#
+# [Hob]
+# RESOURCE_DESCRIPTOR ## PRODUCES
+#
+
+[Ppis]
+ ## CONSUMES
+ gEfiPeiStallPpiGuid
+
+ ## NOTIFY
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+ ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid
+
+ ## NOTIFY
+ gEfiEndOfPeiSignalPpiGuid
+
+ ## PRODUCES
+ gEfiFindFvPpiGuid
+
+[Guids]
+
+ ## PRODUCES ## HOB
+ gEfiMemoryTypeInformationGuid
+
+[Pcd]
+ ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
+
+ ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize
+
+ ## CONSUMES
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo
+ gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid AND gEfiPeiStallPpiGuid
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/BootMode.c b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/BootMode.c index e90c95de78..e902f52ec3 100644 --- a/BraswellPlatformPkg/Common/PlatformPei/BootMode.c +++ b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/BootMode.c @@ -13,8 +13,7 @@ **/
-#include "CommonHeader.h"
-#include "Platform.h"
+#include "PlatformPei.h"
#include "PlatformBaseAddresses.h"
#include "PchRegs.h"
#include <Guid/SetupVariable.h>
@@ -107,7 +106,7 @@ IsBootWithNoChange ( DEBUG ((EFI_D_INFO, "IsFirstBoot = %x , EnableFastBoot= %x. \n", IsFirstBoot, EnableFastBoot));
if ((!IsFirstBoot) && EnableFastBoot) {
- PcdSetBool (PcdBootToFirmwareUserInterface, FALSE);
+ PcdSetBool (PcdBootToFirmwareUserInterface, FALSE);
return TRUE;
} else {
return FALSE;
@@ -164,9 +163,7 @@ UpdateBootMode ( Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
BootMode = BOOT_IN_RECOVERY_MODE;
} else if (IsBootWithNoChange(PeiServices)) {
- if(BootMode != BOOT_ON_S3_RESUME) {
- BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
- }
+ BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
}
#ifdef EFI_DEBUG
diff --git a/BraswellPlatformPkg/Common/PlatformPei/SetupVariableDefault.h b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/SetupVariableDefault.h index c1bfcb22dd..52e6b6c39e 100644 --- a/BraswellPlatformPkg/Common/PlatformPei/SetupVariableDefault.h +++ b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/SetupVariableDefault.h @@ -1226,3 +1226,4 @@ SYSTEM_CONFIGURATION gDefaultSystemConfiguration = { };
#endif // #ifndef _SETUP_VARIABLE_DEFAULT_H
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/Stall.c b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/Stall.c index ce89440e37..f14671f093 100644 --- a/BraswellPlatformPkg/Common/PlatformPei/Stall.c +++ b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/Stall.c @@ -13,7 +13,7 @@ **/
-#include "CommonHeader.h"
+#include "PlatformPei.h"
#include "PlatformBaseAddresses.h"
#include "PchRegs.h"
@@ -83,3 +83,4 @@ Stall ( return EFI_SUCCESS;
}
+
diff --git a/BraswellPlatformPkg/Common/PlatformPei/PreMemory/SystemConfiguration.c b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/SystemConfiguration.c new file mode 100644 index 0000000000..50eb0b1694 --- /dev/null +++ b/BraswellPlatformPkg/Common/PlatformPei/PreMemory/SystemConfiguration.c @@ -0,0 +1,137 @@ +/** @file
+ This PEIM initialize platform for MRC, following action is performed,
+ 1. Initialize GMCH
+ 2. Detect boot mode
+ 3. Detect video adapter to determine whether we need pre-allocated memory
+ 4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.
+ This file contains the main entry point of the PEIM.
+
+ Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PlatformPei.h"
+#include "PlatformBaseAddresses.h"
+#include "PchRegs.h"
+#include <Guid/PlatformInfo.h>
+#include "ChvAccess.h"
+#include <Library/GpioLib.h>
+#include <Guid/Chv2Variable.h>
+#include <Ppi/ChvPlatformPolicyPpi.h>
+#include <Ppi/BoardDetection.h>
+#include <Guid/SetupVariable.h>
+#include "SetupVariableDefault.h"
+
+EFI_STATUS
+GetSetupVariable (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN SYSTEM_CONFIGURATION *SystemConfiguration
+ )
+{
+ UINTN VariableSize;
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
+
+ VariableSize = sizeof (SYSTEM_CONFIGURATION);
+ ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
+
+ Status = (*PeiServices)->LocatePpi (PeiServices,
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ &Variable
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Use normal setup default from NVRAM variable,
+ // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
+ //
+ VariableSize = sizeof(SYSTEM_CONFIGURATION);
+ Status = Variable->GetVariable (Variable,
+ L"Setup",
+ &gEfiSetupVariableGuid,
+ NULL,
+ &VariableSize,
+ SystemConfiguration);
+ return Status;
+}
+
+EFI_STATUS
+GetSystemConfiguration (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN Size;
+ SYSTEM_CONFIGURATION SystemConfiguration;
+
+ //
+ // Get setup variable. This can only be done after BootMode is updated
+ //
+ Status = GetSetupVariable (PeiServices, &SystemConfiguration);
+ Size = sizeof(SYSTEM_CONFIGURATION);
+
+ if(EFI_ERROR(Status)){
+ //
+ // For OC solution, there is no setup variable, so set the SystemConfiguration with default value.
+ //
+ CopyMem(&SystemConfiguration, &gDefaultSystemConfiguration,Size);
+ //
+ // Update the values according to PCD settings
+ //
+
+ //
+ // Platform
+ //
+ SystemConfiguration.TurboModeEnable = PcdGet8(PcdTurboMode);
+
+ //
+ // South Complex
+ //
+ SystemConfiguration.SccSdcardEnabled = PcdGet8(PcdSdcardMode);
+ SystemConfiguration.LpssHsuart0Enabled = PcdGet8(PcdEnableHsuart0);
+ SystemConfiguration.LpssHsuart1Enabled = PcdGet8(PcdEnableHsuart1);
+ SystemConfiguration.PchAzalia = PcdGet8(PcdEnableAzalia);
+ SystemConfiguration.PchSata = PcdGet8(PcdEnableSata);
+ SystemConfiguration.PchUsb30Mode = PcdGet8(PcdEnableXhci);
+ SystemConfiguration.PchLpeEnabled = PcdGet8(PcdEnableLpe);
+ SystemConfiguration.LpssDma0Enabled = PcdGet8(PcdEnableDma0);
+ SystemConfiguration.LpssDma1Enabled = PcdGet8(PcdEnableDma1);
+ SystemConfiguration.LpssI2C0Enabled = PcdGet8(PcdEnableI2C0);
+ SystemConfiguration.LpssI2C1Enabled = PcdGet8(PcdEnableI2C1);
+ SystemConfiguration.LpssI2C2Enabled = PcdGet8(PcdEnableI2C2);
+ SystemConfiguration.LpssI2C3Enabled = PcdGet8(PcdEnableI2C3);
+ SystemConfiguration.LpssI2C4Enabled = PcdGet8(PcdEnableI2C4);
+ SystemConfiguration.LpssI2C5Enabled = PcdGet8(PcdEnableI2C5);
+ SystemConfiguration.LpssI2C6Enabled = PcdGet8(PcdEnableI2C6);
+ SystemConfiguration.ScceMMCEnabled = PcdGet8(PcdEmmcMode);
+ SystemConfiguration.SataInterfaceSpeed = PcdGet8(PcdSataInterfaceSpeed);
+ SystemConfiguration.ISPEn = PcdGet8(ISPEnable);
+ SystemConfiguration.ISPDevSel = PcdGet8(ISPPciDevConfig);
+ SystemConfiguration.PchSata = PcdGet8(PcdEnableSata);
+ SystemConfiguration.MrcDvfsEnable = PcdGet8(PcdDvfsEnable);
+ SystemConfiguration.PnpSettings = PcdGet8(PcdPnpSettings);
+
+ //
+ // North Complex
+ //
+ SystemConfiguration.GTTSize = PcdGet8(PcdGttSize);
+ SystemConfiguration.IgdApertureSize = PcdGet8(PcdApertureSize);
+ SystemConfiguration.IgdDvmt50PreAlloc = PcdGet8(PcdIgdDvmt50PreAlloc);
+ SystemConfiguration.TSEGSizeSel = (UINT8)PcdGet16(PcdMrcInitTsegSize);
+ DEBUG ((EFI_D_INFO, "PeiInitPlatform(): GetSetupVariable returns EFI_NOT_FOUND!! \n"));
+ }
+
+ PcdSetPtr (PcdSystemConfiguration, &Size, &SystemConfiguration);
+ DEBUG ((EFI_D_INFO, "PcdSystemConfiguration size - 0x%x\n", LibPcdGetExSize(&gEfiEdkIIPlatformTokenSpaceGuid, PcdTokenEx(&gEfiEdkIIPlatformTokenSpaceGuid, PcdSystemConfiguration)) ));
+
+ return EFI_SUCCESS;
+}
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