BraswellPlatformPkg: Add dsc and fdf files to BraswellPlatformPkg

Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
author: Guo Mang <mang.guo@intel.com> 2016-08-04 13:30:41 +0800
committer: Guo Mang <mang.guo@intel.com> 2016-08-04 13:30:41 +0800
commit: f71cf3bf29aa216bc72f703815a7f96fb2ca0592 (patch)
tree: de843a0bffd721230acca2bca8709d290c0909b2
parent: 603b6cea5e6b4a97f11dd342b10c9e6704605158 (diff)
download: edk2-platforms-f71cf3bf29aa216bc72f703815a7f96fb2ca0592.tar.xz
4 files changed, 1543 insertions, 0 deletions
diff --git a/BraswellPlatformPkg/PlatformFeatureConfig.dsc b/BraswellPlatformPkg/PlatformFeatureConfig.dsc
new file mode 100644
index 0000000000..83655c72bf
--- /dev/null
+++ b/BraswellPlatformPkg/PlatformFeatureConfig.dsc
@@ -0,0 +1,49 @@
+## @file
+#  Contains the Platform Configuration
+#
+#  Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+DEFINE SEC_ENABLE = FALSE
+DEFINE TPM_ENABLED = FALSE
+DEFINE FTPM_ENABLE = FALSE
+
+DEFINE ACPI50_ENABLE = FALSE
+DEFINE PERFORMANCE_ENABLE = FALSE
+
+
+DEFINE NETWORK_ENABLE = TRUE
+DEFINE NETWORK_IP6_ENABLE = TRUE
+DEFINE NETWORK_ISCSI_ENABLE = FALSE
+DEFINE NETWORK_VLAN_ENABLE = FALSE
+
+DEFINE CLKGEN_CONFIG_EXTRA_ENABLE=TRUE
+DEFINE FSP_BOOT_ENABLE = TRUE
+DEFINE ISH_ENABLE = FALSE
+DEFINE SCSI_ENABLE = TRUE
+DEFINE SECURE_BOOT_ENABLE = TRUE
+DEFINE S3_ENABLE = TRUE
+DEFINE ACPI_ENABLE = TRUE
+DEFINE CAPSULE_ENABLE = TRUE
+DEFINE SIGNED_CAPSULE_ENABLE = FALSE
+DEFINE SMBIOS_ENABLE = TRUE
+DEFINE GOP_DRIVER_ENABLE = TRUE
+DEFINE DATAHUB_ENABLE = TRUE
+DEFINE USB_ENABLE = TRUE
+DEFINE ATA_ENABLE = TRUE
+DEFINE SMM_VARIABLE_ENABLE = TRUE
+DEFINE SATA_ENABLE       = TRUE
+DEFINE PCIESC_ENABLE     = TRUE
+DEFINE ENABLE_FAST_BOOT  = FALSE
+
+
+
diff --git a/BraswellPlatformPkg/PlatformFvBinPkg.fdf b/BraswellPlatformPkg/PlatformFvBinPkg.fdf
new file mode 100644
index 0000000000..5f33697e6d
--- /dev/null
+++ b/BraswellPlatformPkg/PlatformFvBinPkg.fdf
@@ -0,0 +1,762 @@
+## @file
+#  FDF file of Platform.
+#
+#  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+DEFINE FLASH_BASE         = 0xFFC00000     #The base address of the 4Mb FLASH Device.
+DEFINE FLASH_SIZE         = 0x00400000     #The flash size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE   = 0x1000         #The block size in bytes of the 4Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS   = 0x400          #The number of blocks in 4Mb FLASH Device.
+DEFINE FLASH_AREA_BASE_ADDRESS                                = 0xFF800000
+DEFINE FLASH_AREA_SIZE                                        = 0x00800000
+
+DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00000000
+DEFINE FLASH_REGION_VPD_SIZE                                  = 0x0002E000
+
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0002E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE   = 0x00002000
+
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00030000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE     = 0x00030000
+
+DEFINE FLASH_REGION_FVMICROCODE_OFFSET                        = 0x00060000
+DEFINE FLASH_REGION_FVMICROCODE_SIZE                          = 0x00023000
+DEFINE FLASH_REGION_FVMICROCODE_BASE                          = 0xFFC60000
+DEFINE FLASH_REGION_MICROCODE_OFFSET                          = 0x60
+
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00083000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00200000
+DEFINE FLASH_FV_MAIN_BASE                                     = 0xFFC83000
+
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x00283000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x00035000
+DEFINE FLASH_REGION_FV_RECOVERY2_BASE                         = 0xFFE83000
+
+DEFINE FLASH_REGION_FVSHELL_OFFSET                            = 0x002D0000
+DEFINE FLASH_REGION_FVSHELL_SIZE                              = 0x0003F000
+DEFINE FLASH_REGION_FVSHELL_BASE                              = 0xFFED0000
+
+DEFINE FLASH_REGION_FSP_OFFSET                                = 0x00320000
+DEFINE FLASH_REGION_FSP_SIZE                                  = 0x0009E000
+DEFINE FLASH_REGION_FSP_BASE                                  = 0xFFF20000
+
+DEFINE FLASH_REGION_VBT_OFFSET                                = 0x003BE000
+DEFINE FLASH_REGION_VBT_SIZE                                  = 0x00010000
+DEFINE FLASH_REGION_VBT_BASE                                  = 0xFFFBE000
+
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x003CE000
+DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x00032000
+DEFINE FLASH_REGION_FV_RECOVERY_BASE                          = 0xFFFCE000
+
+DEFINE FLASH_FV_RECOVERY_BASE                                 = 0xFFF80000
+DEFINE FLASH_FV_RECOVERY_SIZE                                 = 0x00080000
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.Cht]
+BaseAddress   = $(FLASH_BASE) | gPlatformModuleTokenSpaceGuid.PcdBiosImageBase               #The base address of the 2Mb FLASH Device.
+Size          = $(FLASH_SIZE) | gPlatformModuleTokenSpaceGuid.PcdBiosImageSize               #The flash size in bytes of the 2Mb FLASH Device.
+
+ErasePolarity = 1
+BlockSize     = $(FLASH_BLOCK_SIZE)          #The block size in bytes of the 4Mb FLASH Device.
+NumBlocks     = $(FLASH_NUM_BLOCKS)          #The number of blocks in 4Mb FLASH Device.
+
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF800000
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize = 0x00800000
+SET gIntelSiBasicPkgTokenSpaceGuid.PcdFlashMicroCodeRegionBase = $(FLASH_REGION_FVMICROCODE_BASE)
+SET gIntelSiBasicPkgTokenSpaceGuid.PcdFlashMicroCodeRegionSize = $(FLASH_REGION_FVMICROCODE_SIZE)
+SET gIntelSiBasicPkgTokenSpaceGuid.PcdFlashMicroCodeOffset = $(FLASH_REGION_MICROCODE_OFFSET)
+
+SET gPlatformModuleTokenSpaceGuid.PcdFlashPayloadBase = $(FLASH_REGION_FVSHELL_BASE)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashPayloadSize = $(FLASH_REGION_FVSHELL_SIZE)
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000
+#
+################################################################################
+$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  #  { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x80000
+  0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block
+  0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  #Signature: gEfiAuthenticatedVariableGuid =
+  #  { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+  #Signature: gEfiVariableGuid =
+  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+  #Size: 0x2E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xDF, 0x02, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x00, 0xFD, 0x9F, 0x1B, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+  #
+  # CPU Microcodes
+  #
+
+$(FLASH_REGION_FVMICROCODE_OFFSET)|$(FLASH_REGION_FVMICROCODE_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize
+FV = MICROCODE_FV
+
+  #
+  # Main Block
+  #
+$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+  #
+  # FV Recovery#2
+  #
+$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
+FV = FVRECOVERY2
+
+  #
+  # Shell Application
+  #
+$(FLASH_REGION_FVSHELL_OFFSET)|$(FLASH_REGION_FVSHELL_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize
+FV = FVSHELL
+
+  #
+  # FSP FV
+  #
+$(FLASH_REGION_FSP_OFFSET) | $(FLASH_REGION_FSP_SIZE)
+gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase | gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize
+FILE = ChvFspBinPkg/FspBinary/BswFsp$(TARGET).fd
+
+  #
+  # VBT FV for FSP
+  #
+$(FLASH_REGION_VBT_OFFSET) | $(FLASH_REGION_VBT_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvVbtBase | gPlatformModuleTokenSpaceGuid.PcdFlashFvVbtSize
+FV = FVVBT
+
+  #
+  # FV Recovery
+  #
+$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
+FV = FVRECOVERY
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.MICROCODE_FV]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = FALSE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
+  $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/MicrocodeUpdates.bin
+}
+
+[FV.FVVBT]
+BlockSize          = 0x00001000
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = e17429bd-2b57-40a7-bce8-bd219884a770
+
+!if $(GOP_DRIVER_ENABLE) == TRUE
+FILE FREEFORM = EE62C785-3CF3-4027-8672-6DE4E7FF4317 {
+  SECTION RAW = $(WORKSPACE)/Platform/$(PLATFORM_PACKAGE)/Board/BraswellCR/Vbt/Vbt_BSW_CR.bin
+  SECTION UI = "IntelGopVbtCR"
+}
+
+#
+# HDMI on Port B, DP and HDMI compatible on Port C, DP and HDMI compatible on Port D.
+#
+FILE FREEFORM = CFF9CF38-AE87-440d-80A9-004701FE8D01 {
+  SECTION RAW = $(WORKSPACE)/Platform/$(PLATFORM_PACKAGE)/Board/BraswellCherryHill/Vbt/Vbt_HDMIPB_DPHDMIPC_DPHDMIPD.bin
+  SECTION UI = "IntelGopVbtHdmiDp"
+}
+!endif
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.FVRECOVERY_COMPONENTS]
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+INF  ChvRefCodePkg/CherryViewSoc/SouthCluster/Usb/Pei/PchUsb.inf
+INF  MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf
+INF  MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
+INF  MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
+INF  FatPkg/FatPei/FatPei.inf
+
+[FV.FVRECOVERY2]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
+
+INF $(PLATFORM_PACKAGE)/Common/PlatformPei/PostSilicon/PostSiliconInit.inf
+
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/SmmControl/Pei/SmmControl.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/NorthCluster/SmmAccess/Pei/SmmAccess.inf
+INF IntelSiliconBasicPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/CPU/CpuS3/MpS3.inf
+
+!if ($(TPM_ENABLED) == TRUE)
+INF $(PLATFORM_RC_PACKAGE)/Txe/fTPM/Pei/fTPMInitPei.inf
+INF  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf
+INF  SecurityPkg/Tcg/TrEEPei/TrEEPei.inf
+!endif
+
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+!if $(ACPI50_ENABLE) == TRUE
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
+!endif
+
+FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {
+  SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid}
+  SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF {    # LZMA COMPRESS GUID
+    SECTION FV_IMAGE = FVRECOVERY_COMPONENTS
+  }
+}
+
+[FV.FVRECOVERY]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270091
+
+INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
+INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+!if $(CAPSULE_ENABLE) == TRUE
+#
+# Capsule support
+#
+INF  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+!if $(DXE_ARCHITECTURE) == X64
+INF  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf
+!endif
+!endif
+
+INF $(PLATFORM_PACKAGE)/Common/PlatformPei/PlatformPei.inf
+INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
+
+[FV.FVMAIN]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+  #
+  # EDK II Related Platform codes
+  #
+
+INF RuleOverride = FVIMAGE USE = X64 Core/Bin/AsBuildCOREDXEFVX64.inf
+
+INF $(PLATFORM_PACKAGE)/Common/PlatformDxe/PlatformDxe.inf
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+INF BraswellPlatformPkg/Common/PcdConfigHook/DxePcdConfigHook.inf
+!if $(ACPI50_ENABLE) == TRUE
+INF RuleOverride = FVIMAGE USE = X64 Core/Bin/AsBuildCOREDXEACPI50FVX64.inf
+!endif
+
+
+INF IntelSiliconBasicPkg/CpuInit/MpCpu.inf
+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+INF  BraswellPlatformPkg/Common/Flash/SpiFlashParts/MX25/MX25.inf
+!if $(SMM_VARIABLE_ENABLE) == TRUE
+  # Smm solution for variable
+  INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/Spi/Smm/PchSpiSmm.inf
+  INF BraswellPlatformPkg/Common/Flash/SpiDeviceDxe/SpiDeviceSmm.inf
+  INF BraswellPlatformPkg/Common/Flash/SpiDeviceDxe/SpiDeviceSmmDxe.inf
+  INF BraswellPlatformPkg/Common/Flash/FvbRuntimeDxe/FvbSmm.inf
+  INF BraswellPlatformPkg/Common/Flash/FvbRuntimeDxe/FvbSmmDxe.inf
+!else
+  # Runtime solution for variable
+  INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/Spi/RuntimeDxe/PchSpiRuntime.inf
+  INF BraswellPlatformPkg/Common/SpiDeviceDxe/SpiDeviceDxe.inf
+  INF BraswellPlatformPkg/Common/FvbRuntimeDxe/FvbRuntimeDxe.inf
+!endif
+
+INF $(PLATFORM_PACKAGE)/Common/Setup/PlatformSetupDxe.inf
+
+INF $(PLATFORM_RC_PACKAGE)/Platform/PlatformEmmc/Dxe/PlatformEmmcDxe.inf
+
+#
+# EDK II Related Silicon codes
+#
+!if $(SEC_ENABLE) == TRUE
+!endif
+
+
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/SmmControl/RuntimeDxe/SmmControl.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/Reset/RuntimeDxe/PchReset.inf
+INF $(PCH_INIT_ROOT)/Dxe/PchInitDxe.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
+
+INF IntelSiliconBasicPkg/PciHostBridge/PciHostBridge.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/NorthCluster/SmmAccess/Dxe/SmmAccess.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/NorthCluster/ChvInit/Dxe/ChvInit.inf
+
+!if $(SEC_ENABLE) == TRUE
+!endif
+
+!if $(TPM_ENABLED) == TRUE
+INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf
+INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf
+INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
+INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TrEESmm/TrEESmm.inf
+!endif
+!if ($(TPM_ENABLED) == TRUE)||($(FTPM_ENABLE) == TRUE)
+INF SecurityPkg/Tcg/MemoryOverwriteControl/TcgMor.inf
+INF SecurityPkg/Tcg/TrEEDxe/TrEEDxe.inf
+!if $(FTPM_ENABLE) == TRUE
+INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_RC_PACKAGE)/Txe/fTPM/Smm/FtpmSmm.inf
+INF SecurityPkg/Tcg/TrEEConfig/TrEEConfigDxe.inf
+!endif
+!endif
+
+#
+# EDK II Related Platform codes
+#
+INF $(PLATFORM_PACKAGE)/Common/Acpi/AcpiSmm/AcpiSmm.inf
+INF $(PLATFORM_PACKAGE)/Common/Feature/PciPlatform/PciPlatform.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/CPU/SampleCode/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+INF $(PLATFORM_PACKAGE)/Common/PlatformSmm/PlatformSmm.inf
+
+!if $(GOP_DRIVER_ENABLE) == TRUE
+INF $(PLATFORM_PACKAGE)/Common/FspSupport/GraphicsOutputDxe/GraphicsOutputDxe.inf
+!endif
+
+#INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/Pnp/Dxe/PnpDxe.inf
+
+#
+# SMM
+#
+INF IntelSiliconBasicPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+INF IntelSiliconBasicPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/CPU/PowerManagement/Smm/PowerManagement.inf
+
+#
+# ACPI
+#
+#INF $(PLATFORM_RC_PACKAGE)/DigitalThermalSensor/Smm/DigitalThermalSensor.inf
+INF RuleOverride = ACPITABLE2 $(PLATFORM_RC_PACKAGE)/CherryViewSoc/CPU/AcpiTables/CpuAcpiTables.inf
+INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
+INF $(PLATFORM_PACKAGE)/Common/Acpi/AcpiPlatform/AcpiPlatform.inf
+INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_PACKAGE)/Board/BraswellCR/Acpi/Acpi.inf
+INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_PACKAGE)/Board/BraswellCherryHill/Acpi/Acpi.inf
+
+#
+# PCI
+#
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/NorthCluster/ISPDxe/ISPDxe.inf
+
+#
+# Network Modules
+#
+!if $(NETWORK_ENABLE) == TRUE
+  FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C {
+    SECTION PE32 = RealtekUndiPkg/Rtl8111gUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi
+    SECTION UI = "UNDI"
+  }
+
+INF RuleOverride = FVIMAGE USE = X64 Core/Bin/AsBuildCOREDXENETWORKFVX64.inf
+!endif
+
+INF IntelSiliconBasicPkg/SerialDxe/SerialDxe.inf
+
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/SDControllerDxe/MmcHostDxe.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/SDMediaDeviceDxe/MmcMediaDeviceDxe.inf
+
+#
+# IDE/SCSI/AHCI
+#
+!if $(SATA_ENABLE) == TRUE
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/SouthCluster/SataController/Dxe/SataController.inf
+!endif
+
+#
+# SMBIOS
+#
+INF $(PLATFORM_PACKAGE)/Common/Feature/SmBiosMiscDxe/SmbiosMiscDxe.inf
+INF $(PLATFORM_RC_PACKAGE)/CherryViewSoc/NorthCluster/SmBiosMemory/Dxe/SmBiosMemory.inf
+
+#
+# Logo
+#
+FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
+SECTION RAW = BraswellPlatformPkg/Common/Feature/Logo/Logo.bmp
+SECTION UI = "Logo"
+}
+
+[FV.FVSHELL]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) {
+#          SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi
+# LZMA Compress
+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+         #SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi
+         SECTION PE32 = ShellBinPkg/UefiShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi
+       }
+     }
+
+[FV.FVMAIN_COMPACT]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+# LZMA Compress
+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+     }
+
+[FV.SETUP_DATA]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+#NumBlocks         = 0x10
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+[FV.Bios_Update_Data]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = 4A538818-5AE0-4eb2-B2EB-488B23657022 {
+       SECTION FV_IMAGE = FVMAIN_COMPACT
+     }
+
+!if $(CAPSULE_ENABLE) == TRUE
+[FV.BiosUpdateCargo]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+INF  IntelFrameworkModulePkg/Universal/FirmwareVolume/UpdateDriverDxe/UpdateDriverDxe.inf
+
+FILE RAW = 283FA2EE-532C-484d-9383-9F93B36F0B7E {
+       FV = Bios_Update_Data
+     }
+
+FILE RAW = 98B8D59B-E8BA-48EE-98DD-C295392F1EDB {
+   BraswellPlatformPkg/Common/Feature/BiosUpdateConfig/BiosUpdateConfig.ini
+   }
+
+
+[FV.BiosUpdate]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE FV_IMAGE = EDBEDF47-6EA3-4512-83C1-70F4769D4BDE {
+!if $(SIGNED_CAPSULE_ENABLE) == TRUE
+  #
+  # Signed Section
+  #
+  SECTION GUIDED A7717414-C616-4977-9420-844712A735BF AUTH_STATUS_VALID = TRUE {
+!endif
+    #
+    # Compressed Section
+    #
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = BiosUpdateCargo
+    }
+!if $(SIGNED_CAPSULE_ENABLE) == TRUE
+  }
+!endif
+}
+
+[Capsule.Capsule_Reset]
+#
+# gEfiCapsuleGuid supported by platform
+# { 0x3B6686BD, 0x0D76, 0x4030, { 0xB7, 0x0E, 0xB5, 0x51, 0x9E, 0x2F, 0xC5, 0xA0 }}
+#
+CAPSULE_GUID  = 3B6686BD-0D76-4030-B70E-B5519E2FC5A0
+CAPSULE_FLAGS = PersistAcrossReset,InitiateReset
+CAPSULE_HEADER_SIZE = 0x20
+
+FV = BiosUpdate
+!endif
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+!include Include/Build/BuildRule.fdf
+
diff --git a/BraswellPlatformPkg/PlatformPcdIA32.dsc b/BraswellPlatformPkg/PlatformPcdIA32.dsc
new file mode 100644
index 0000000000..6b0c44f900
--- /dev/null
+++ b/BraswellPlatformPkg/PlatformPcdIA32.dsc
@@ -0,0 +1,366 @@
+## @file
+#  Platform description.
+#
+#  Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# FSP Configuration
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+  gFspWrapperTokenSpaceGuid.PcdTemporaryRamSize|0x00020000
+
+[PcdsFixedAtBuild.IA32]
+  !if $(PERFORMANCE_ENABLE) == TRUE
+    gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x1600
+  !else
+    gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2600
+  !endif
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC60000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00023000
+  gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFC00000
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00400000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF20000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x0009E000
+  gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize|0x300
+
+[PcdsPatchableInModule.common]
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000
+
+##################################################################################
+#
+# Debug
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE
+  !if $(TARGET) == RELEASE
+    gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+  !else
+    gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+  !endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+
+[PcdsFixedAtBuild.common]
+  !if $(TARGET) == RELEASE
+    gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+    gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+  !else
+    gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+    gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  !endif
+
+[PcdsFixedAtBuild.IA32]
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+
+[PcdsPatchableInModule.common]
+  # UART 16550
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80380546
+
+##################################################################################
+#
+# Security
+#
+##################################################################################
+[PcdsFixedAtBuild.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+
+  ## Pcd for OptionRom.
+  #  Image verification policy settings:
+  #  ALWAYS_EXECUTE                         0x00000000
+  #  NEVER_EXECUTE                          0x00000001
+  #  ALLOW_EXECUTE_ON_SECURITY_VIOLATION    0x00000002
+  #  DEFER_EXECUTE_ON_SECURITY_VIOLATION    0x00000003
+  #  DENY_EXECUTE_ON_SECURITY_VIOLATION     0x00000004
+  #  QUERY_USER_ON_SECURITY_VIOLATION       0x00000005
+  gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy | 0x00000004
+!endif
+
+[PcdsDynamicExDefault.common.DEFAULT]
+!if $(TPM_ENABLED) == TRUE
+  ## Put Ptt guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+  ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }
+  ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }
+  ## TPM2.0Ptt { 0x72cd3a7b, 0xfea5, 0x4f5e, { 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13 } }
+  #gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0xb6, 0xe5, 0x01, 0x8b, 0x19, 0x4f, 0xe8, 0x46, 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc}
+  #gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|FALSE
+
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEEAvailableEventLogs|0x00000001
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEEHashAlgorithmBitmap|0
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEESupportedEventLogs|0xFFFFFFFF
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEEProtocolVersion|0x0001
+
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2ScrtmPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
+!endif
+
+[PcdsDynamicDefault.common.DEFAULT]
+ !if $(TPM_ENABLED) == TRUE
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyChangeAuthPlatform|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyControlPlatform|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyControlEndorsement|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyControlOwner|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2ChangeEps|0
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2ChangePps|0
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2Clear|0
+!endif
+
+##################################################################################
+#
+# SMBIOS
+#
+##################################################################################
+[PcdsPatchableInModule.common]
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosVersion|"Cherryview Platform BIOS"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemUuid|{0xa5, 0x00, 0x02, 0x88, 0x64, 0x62, 0x45, 0x24, 0x98, 0x6a, 0x9b, 0x77, 0x37, 0xe3, 0x15, 0xcf}
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemManufacturer|"Intel Corporation"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemVersion|"0.1"|VOID* |0x40
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemSerialNumber|"112233445566"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardManufacturer|"Intel Corp."|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardVersion|"FAB"|VOID* |0x20
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardSerialNumber|"1"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisManufacturer|"Intel Corporation"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisVersion|"0.1"|VOID* |0x20
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisSerialNumber|"serial"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisAssetTag|"Asset Tag"|VOID* |0x20
+
+##################################################################################
+#
+# Console & HII
+#
+##################################################################################
+[PcdsDynamicExDefault.common.DEFAULT]
+  ## This PCD defines the video horizontal resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
+  ## This PCD defines the video vertical resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
+
+  ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31|UINT32|0x40000006
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+  ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100|UINT32|0x40000007
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+  ## The PCD is used to specify the video horizontal resolution of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800|UINT32|0x50000001
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+  ## The PCD is used to specify the video vertical resolution of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600|UINT32|0x50000002
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+  ## The PCD is used to specify the console output column of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100|UINT32|0x50000003
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
+  ## The PCD is used to specify the console output column of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31|UINT32|0x50000004
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+
+[PcdsDynamicHii.common.DEFAULT]
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|L"ConOutConfig"|gClientCommonModuleTokenSpaceGuid|0x0|100
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|L"ConOutConfig"|gClientCommonModuleTokenSpaceGuid|0x4|31
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiCHVTokenSpaceGuid.PcdBmpImageGuid |{0x87, 0x8A, 0xC2, 0xCC, 0x53, 0x43, 0x46, 0xF2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}
+
+[PcdsPatchableInModule.common]
+  gPlatformModuleTokenSpaceGuid.PcdCustomizedVbtFile|{0xFF, 0xFF, 0xFF, 0xFF} |4  # Reserve n bytes for customized vbt
+
+[PcdsFeatureFlag.common]
+gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE
+
+##################################################################################
+#
+# Variable
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
+
+[PcdsFixedAtBuild.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x7000
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+
+[PcdsPatchableInModule.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0
+
+##################################################################################
+#
+# Boot
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  # IA32 and X64 select
+   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
+
+  # Recovery
+  gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
+
+[PcdsPatchableInModule.common]
+  ## This PCD specifies whether to use the optimized timing for best PS2 detection performance.
+  #  Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
+  #gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE|BOOLEAN|0x3000000b
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
+
+  !if $(ENABLE_FAST_BOOT)
+    gPlatformModuleTokenSpaceGuid.PcdEnableFastBoot|TRUE
+  !else
+    gPlatformModuleTokenSpaceGuid.PcdEnableFastBoot|FALSE
+  !endif
+
+[PcdsDynamicExHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+  gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gPlatformModuleTokenSpaceGuid.PcdBootToFirmwareUserInterface|FALSE
+
+##################################################################################
+#
+# ACPI
+#
+##################################################################################
+[PcdsFixedAtBuild.common]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x200000
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFixedAtBuild.common]
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|31
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x40
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x02
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x400
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFF80
+
+[PcdsPatchableInModule.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"Intel "
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445
+
+##################################################################################
+#
+# SMM
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileEnable|TRUE
+
+
+[PcdsFeatureFlag.X64]
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
+
+##################################################################################
+#
+# Misc
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+  ## This PCD specifies whether PS2 keyboard does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
+  ## This PCD specifies whether PS2 mouse does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE
+
+[PcdsFixedAtBuild.common]
+  gChvRefCodePkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|7
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
+!endif
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+
+[PcdsPatchableInModule.common]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE)
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|0x00010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Intel Corporation"|VOID* |0x80
+  gEfiEdkIIPlatformTokenSpaceGuid.PcdSsidSvid|0x12348086
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration|{0x0}|VOID*|0x3A0
+  gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo|{0x0}|VOID*|0x100
+
+
+
+
+
+
+
+
diff --git a/BraswellPlatformPkg/PlatformPcdX64.dsc b/BraswellPlatformPkg/PlatformPcdX64.dsc
new file mode 100644
index 0000000000..eb0e0924ce
--- /dev/null
+++ b/BraswellPlatformPkg/PlatformPcdX64.dsc
@@ -0,0 +1,366 @@
+## @file
+#  Platform description.
+#
+#  Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# FSP Configuration
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+  gFspWrapperTokenSpaceGuid.PcdTemporaryRamSize|0x00020000
+
+[PcdsFixedAtBuild.IA32]
+  !if $(PERFORMANCE_ENABLE) == TRUE
+    gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x1600
+  !else
+    gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x2600
+  !endif
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFC60000
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00023000
+  gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFFC00000
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00400000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF20000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x0009E000
+  gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize|0x300
+
+[PcdsPatchableInModule.common]
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000
+
+##################################################################################
+#
+# Debug
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE
+  !if $(TARGET) == RELEASE
+    gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+  !else
+    gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+  !endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+
+[PcdsFixedAtBuild.common]
+  !if $(TARGET) == RELEASE
+    gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+    gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+  !else
+    gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+    gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  !endif
+
+[PcdsFixedAtBuild.X64]
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+
+[PcdsPatchableInModule.common]
+  # UART 16550
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x3F8
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
+
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80380546
+
+##################################################################################
+#
+# Security
+#
+##################################################################################
+[PcdsFixedAtBuild.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
+
+  ## Pcd for OptionRom.
+  #  Image verification policy settings:
+  #  ALWAYS_EXECUTE                         0x00000000
+  #  NEVER_EXECUTE                          0x00000001
+  #  ALLOW_EXECUTE_ON_SECURITY_VIOLATION    0x00000002
+  #  DEFER_EXECUTE_ON_SECURITY_VIOLATION    0x00000003
+  #  DENY_EXECUTE_ON_SECURITY_VIOLATION     0x00000004
+  #  QUERY_USER_ON_SECURITY_VIOLATION       0x00000005
+  gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy | 0x00000004
+!endif
+
+[PcdsDynamicExDefault.common.DEFAULT]
+!if $(TPM_ENABLED) == TRUE
+  ## Put Ptt guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+  ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }
+  ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }
+  ## TPM2.0Ptt { 0x72cd3a7b, 0xfea5, 0x4f5e, { 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13 } }
+  #gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0xb6, 0xe5, 0x01, 0x8b, 0x19, 0x4f, 0xe8, 0x46, 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc}
+  #gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|FALSE
+
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEEAvailableEventLogs|0x00000001
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEEHashAlgorithmBitmap|0
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEESupportedEventLogs|0xFFFFFFFF
+  gEfiSecurityPkgTokenSpaceGuid.PcdTrEEProtocolVersion|0x0001
+
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2ScrtmPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
+!endif
+
+[PcdsDynamicDefault.common.DEFAULT]
+ !if $(TPM_ENABLED) == TRUE
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyChangeAuthPlatform|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyControlPlatform|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyControlEndorsement|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2HierarchyControlOwner|1
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2ChangeEps|0
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2ChangePps|0
+  gClientCommonModuleTokenSpaceGuid.PcdTpm2Clear|0
+!endif
+
+##################################################################################
+#
+# SMBIOS
+#
+##################################################################################
+[PcdsPatchableInModule.common]
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBiosVersion|"Cherryview Platform BIOS"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemUuid|{0xa5, 0x00, 0x02, 0x88, 0x64, 0x62, 0x45, 0x24, 0x98, 0x6a, 0x9b, 0x77, 0x37, 0xe3, 0x15, 0xcf}
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemManufacturer|"Intel Corporation"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemVersion|"0.1"|VOID* |0x40
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSSystemSerialNumber|"112233445566"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardManufacturer|"Intel Corp."|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardVersion|"FAB"|VOID* |0x20
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSBoardSerialNumber|"1"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisManufacturer|"Intel Corporation"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisVersion|"0.1"|VOID* |0x20
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisSerialNumber|"serial"|VOID* |0x80
+  gPlatformModuleTokenSpaceGuid.PcdSMBIOSChassisAssetTag|"Asset Tag"|VOID* |0x20
+
+##################################################################################
+#
+# Console & HII
+#
+##################################################################################
+[PcdsDynamicExDefault.common.DEFAULT]
+  ## This PCD defines the video horizontal resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
+  ## This PCD defines the video vertical resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
+
+  ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31|UINT32|0x40000006
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+  ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100|UINT32|0x40000007
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+  ## The PCD is used to specify the video horizontal resolution of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800|UINT32|0x50000001
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+  ## The PCD is used to specify the video vertical resolution of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600|UINT32|0x50000002
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+  ## The PCD is used to specify the console output column of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100|UINT32|0x50000003
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
+  ## The PCD is used to specify the console output column of text setup.
+  #gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31|UINT32|0x50000004
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE
+
+[PcdsFixedAtBuild.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+
+[PcdsDynamicHii.common.DEFAULT]
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|L"ConOutConfig"|gClientCommonModuleTokenSpaceGuid|0x0|100
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|L"ConOutConfig"|gClientCommonModuleTokenSpaceGuid|0x4|31
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiCHVTokenSpaceGuid.PcdBmpImageGuid |{0x87, 0x8A, 0xC2, 0xCC, 0x53, 0x43, 0x46, 0xF2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}
+
+[PcdsPatchableInModule.common]
+  gPlatformModuleTokenSpaceGuid.PcdCustomizedVbtFile|{0xFF, 0xFF, 0xFF, 0xFF} |4  # Reserve n bytes for customized vbt
+
+[PcdsFeatureFlag.common]
+gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE
+
+##################################################################################
+#
+# Variable
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
+
+[PcdsFixedAtBuild.common]
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x7000
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+
+[PcdsPatchableInModule.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0
+
+##################################################################################
+#
+# Boot
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  # IA32 and X64 select
+   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+  # Recovery
+  gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
+
+[PcdsPatchableInModule.common]
+  ## This PCD specifies whether to use the optimized timing for best PS2 detection performance.
+  #  Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
+  #gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE|BOOLEAN|0x3000000b
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
+
+  !if $(ENABLE_FAST_BOOT)
+    gPlatformModuleTokenSpaceGuid.PcdEnableFastBoot|TRUE
+  !else
+    gPlatformModuleTokenSpaceGuid.PcdEnableFastBoot|FALSE
+  !endif
+
+[PcdsDynamicExHii.common.DEFAULT]
+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+  gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gPlatformModuleTokenSpaceGuid.PcdBootToFirmwareUserInterface|FALSE
+
+##################################################################################
+#
+# ACPI
+#
+##################################################################################
+[PcdsFixedAtBuild.common]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x200000
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+[PcdsFixedAtBuild.common]
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|31
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x40
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x02
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x400
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFF80
+
+[PcdsPatchableInModule.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"Intel "
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445
+
+##################################################################################
+#
+# SMM
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmProfileEnable|TRUE
+
+
+[PcdsFeatureFlag.X64]
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+
+[PcdsFixedAtBuild.common]
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
+
+##################################################################################
+#
+# Misc
+#
+##################################################################################
+[PcdsFeatureFlag.common]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+  ## This PCD specifies whether PS2 keyboard does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
+  ## This PCD specifies whether PS2 mouse does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE
+
+[PcdsFixedAtBuild.common]
+  gChvRefCodePkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|7
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
+!endif
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
+
+[PcdsPatchableInModule.common]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE)
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|0x00010000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Intel Corporation"|VOID* |0x80
+  gEfiEdkIIPlatformTokenSpaceGuid.PcdSsidSvid|0x12348086
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiEdkIIPlatformTokenSpaceGuid.PcdSystemConfiguration|{0x0}|VOID*|0x3A0
+  gEfiEdkIIPlatformTokenSpaceGuid.PcdPlatformInfo|{0x0}|VOID*|0x100
+
+
+
+
+
+
+
+
author	Guo Mang <mang.guo@intel.com>	2016-08-04 13:30:41 +0800
committer	Guo Mang <mang.guo@intel.com>	2016-08-04 13:30:41 +0800
commit	f71cf3bf29aa216bc72f703815a7f96fb2ca0592 (patch)
tree	de843a0bffd721230acca2bca8709d290c0909b2
parent	603b6cea5e6b4a97f11dd342b10c9e6704605158 (diff)
download	edk2-platforms-f71cf3bf29aa216bc72f703815a7f96fb2ca0592.tar.xz