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| author | Olivier Martin <olivier.martin@arm.com> | 2014-06-03 16:42:18 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-06-03 16:42:18 +0000 |
| commit | ec17f0f56a1b6345baef5d73e6ed7bc2016f4b78 (patch) | |
| tree | 679af189e6de724c3f925ec058019bb3346914e6 /ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c | |
| parent | 27331bff97f4fb36bee3aad8e010576ca641304e (diff) | |
| download | edk2-platforms-ec17f0f56a1b6345baef5d73e6ed7bc2016f4b78.tar.xz | |
ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt handling
See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in
"Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions"
Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c')
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c b/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c index 55a7132193..d7d33fb492 100644 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c +++ b/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c @@ -209,7 +209,7 @@ InitializeExceptions ( ArmWriteVBar (PcdGet32(PcdCpuVectorBaseAddress));
} else {
// The Vector table must be 32-byte aligned
- ASSERT(((UINT32)ExceptionHandlersStart & ((1 << 5)-1)) == 0);
+ ASSERT(((UINT32)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
ArmWriteVBar ((UINT32)ExceptionHandlersStart);
|