ArmPkg/CpuPei: Get the System Memory from the Resource Memory HOB

Declare the system memory provided by the first Resource Memory HOB
as cached memory to the MMU.
All the remaining memory space is declared as Device Memory.


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11861 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 72 insertions, 18 deletions

diff --git a/ArmPkg/Drivers/CpuPei/CpuPei.c b/ArmPkg/Drivers/CpuPei/CpuPei.c
index 5e26244354..d06ecd743e 100755
--- a/ArmPkg/Drivers/CpuPei/CpuPei.c
+++ b/ArmPkg/Drivers/CpuPei/CpuPei.c
@@ -1,6 +1,7 @@
 /**@file

 

 Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>

 This program and the accompanying materials                          

 are licensed and made available under the terms and conditions of the BSD License         

 which accompanies this distribution.  The full text of the license may be found at        

@@ -45,11 +46,40 @@ Abstract:
 #define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK

 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED

 

+EFI_STATUS

+FindMainMemory(

+  OUT UINT32    *PhysicalBase,

+  OUT UINT32    *Length

+  )

+{

+  EFI_PEI_HOB_POINTERS      NextHob;

+

+  // look at the resource descriptor hobs, choose the first system memory one

+  NextHob.Raw = GetHobList ();

+  while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {

+    if(NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)

+    {

+      *PhysicalBase = (UINT32)NextHob.ResourceDescriptor->PhysicalStart;

+      *Length = (UINT32)NextHob.ResourceDescriptor->ResourceLength;

+      return EFI_SUCCESS;

+    }

+

+    NextHob.Raw = GET_NEXT_HOB (NextHob);

+  }

+

+  return EFI_NOT_FOUND;

+}

+

 VOID

-JamArmMmuConfig ( VOID )

+ConfigureMmu ( VOID )

 {

+  EFI_STATUS                 Status;

+  UINTN                         Idx;

   UINT32                        CacheAttributes;

-  ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[3];

+  UINT32                        SystemMemoryBase;

+  UINT32                        SystemMemoryLength;

+  UINT32                        SystemMemoryLastAddress;

+  ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[4];

   VOID                          *TranslationTableBase;

   UINTN                         TranslationTableSize;

 

@@ -59,24 +89,48 @@ JamArmMmuConfig ( VOID )
     CacheAttributes = DDR_ATTRIBUTES_UNCACHED;

   }

 

-  // DDR

-  MemoryTable[0].PhysicalBase = 0;

-  MemoryTable[0].VirtualBase  = 0;

-  MemoryTable[0].Length       = 0x10000000;

-  MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

+  Idx = 0;

+  

+  // Main Memory

+  Status = FindMainMemory (&SystemMemoryBase, &SystemMemoryLength);

+  ASSERT_EFI_ERROR (Status);

+

+  SystemMemoryLastAddress = SystemMemoryBase + (SystemMemoryLength-1);

+

+  // if system memory does not begin at 0

+  if(SystemMemoryBase > 0) {

+    MemoryTable[Idx].PhysicalBase = 0;

+    MemoryTable[Idx].VirtualBase  = 0;

+    MemoryTable[Idx].Length       = SystemMemoryBase;

+    MemoryTable[Idx].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

+    Idx++;

+  }

 

-  // SOC Registers. L3 interconnects

-  MemoryTable[1].PhysicalBase = 0x10000000;

-  MemoryTable[1].VirtualBase  = 0x10000000;

-  MemoryTable[1].Length       = 0xF0000000;

-  MemoryTable[1].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

+  MemoryTable[Idx].PhysicalBase = SystemMemoryBase;

+  MemoryTable[Idx].VirtualBase  = SystemMemoryBase;

+  MemoryTable[Idx].Length       = SystemMemoryLength;

+  MemoryTable[Idx].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

+  Idx++;

+

+  // if system memory does not go to the last address (0xFFFFFFFF)

+  if( SystemMemoryLastAddress < MAX_ADDRESS ) {

+    MemoryTable[Idx].PhysicalBase = SystemMemoryLastAddress + 1;

+    MemoryTable[Idx].VirtualBase  = MemoryTable[Idx].PhysicalBase;

+    MemoryTable[Idx].Length       = MAX_ADDRESS - MemoryTable[Idx].PhysicalBase + 1;

+    MemoryTable[Idx].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;

+    Idx++;

+  }

 

   // End of Table

-  MemoryTable[2].PhysicalBase = 0;

-  MemoryTable[2].VirtualBase  = 0;

-  MemoryTable[2].Length       = 0;

-  MemoryTable[2].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

-  

+  MemoryTable[Idx].PhysicalBase = 0;

+  MemoryTable[Idx].VirtualBase  = 0;

+  MemoryTable[Idx].Length       = 0;

+  MemoryTable[Idx].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

+   

+  DEBUG ((EFI_D_INFO, "Enabling MMU, setting 0x%08x + %d MB to %a\n",

+    SystemMemoryBase, SystemMemoryLength/1024/1024,

+    (CacheAttributes == DDR_ATTRIBUTES_CACHED) ? "cacheable" : "uncacheable"));

+

   ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);

   

   BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);

@@ -109,7 +163,7 @@ Returns:
   // Enable program flow prediction, if supported.

   ArmEnableBranchPrediction ();

 

-  JamArmMmuConfig();

+  ConfigureMmu();

 

   return EFI_SUCCESS;

 }