summaryrefslogtreecommitdiff
path: root/ArmPkg/Drivers
diff options
context:
space:
mode:
authoroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2012-07-04 20:23:21 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2012-07-04 20:23:21 +0000
commitce88684e2af0103e7ffaea58a26b3fae16f70367 (patch)
tree466d7fb7d4a2060ac9d18cc908f904559adb7579 /ArmPkg/Drivers
parent3bb46df2a3456929e2776470a5547e4827937853 (diff)
downloadedk2-platforms-ce88684e2af0103e7ffaea58a26b3fae16f70367.tar.xz
ARM Packages: Fixed mispellings
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13502 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers')
-rw-r--r--ArmPkg/Drivers/CpuDxe/Mmu.c2
-rw-r--r--ArmPkg/Drivers/PL390Gic/PL390GicSec.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index f54350b5a2..7bed1f69c0 100644
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -784,7 +784,7 @@ ConvertSectionToPages (
// formulate page table entry, Domain=0, NS=0
PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
- // write the page table entry out, repalcing section entry
+ // write the page table entry out, replacing section entry
FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
return EFI_SUCCESS;
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 25038bd63f..e47e23d581 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -99,7 +99,7 @@ ArmGicEnableInterruptInterface (
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
// Enable CPU interface in Secure world
- // Enable CPU inteface in Non-secure World
+ // Enable CPU interface in Non-secure World
// Signal Secure Interrupts to CPU using FIQ line *
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
ARM_GIC_ICCICR_ENABLE_SECURE |