Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib.h and fixed a lot of issues with Xcode building.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 204 insertions, 0 deletions

diff --git a/ArmPkg/Include/Drivers/PL341Dmc.h b/ArmPkg/Include/Drivers/PL341Dmc.h
new file mode 100644
index 0000000000..68b8be444a
--- /dev/null
+++ b/ArmPkg/Include/Drivers/PL341Dmc.h
@@ -0,0 +1,84 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PL341DMC_H_
+#define PL341DMC_H_
+
+
+struct pl341_dmc_config {
+    UINTN	base;           // base address for the controller
+    UINTN	has_qos;        // has QoS registers
+    UINTN	max_chip;       // number of memory chips accessible
+    UINT32	refresh_prd;
+    UINT32	cas_latency;
+    UINT32	write_latency;
+    UINT32	t_mrd;
+    UINT32	t_ras;
+    UINT32	t_rc;
+    UINT32	t_rcd;
+    UINT32	t_rfc;
+    UINT32	t_rp;
+    UINT32	t_rrd;
+    UINT32	t_wr;
+    UINT32	t_wtr;
+    UINT32	t_xp;
+    UINT32	t_xsr;
+    UINT32	t_esr;
+    UINT32	memory_cfg;
+    UINT32	memory_cfg2;
+    UINT32	memory_cfg3;
+    UINT32	chip_cfg0;
+    UINT32	chip_cfg1;
+    UINT32	chip_cfg2;
+    UINT32	chip_cfg3;
+    UINT32	t_faw;
+};
+
+/* Memory config bit fields */
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9      0x1
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10     0x2
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11     0x3
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12     0x4
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11        (0x0 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12        (0x1 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13        (0x2 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14        (0x3 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15        (0x4 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16        (0x5 << 3)
+#define DMC_MEMORY_CONFIG_BURST_2               (0x1 << 15)
+#define DMC_MEMORY_CONFIG_BURST_4               (0x2 << 15)
+#define DMC_MEMORY_CONFIG_BURST_8               (0x3 << 15)
+#define DMC_MEMORY_CONFIG_BURST_16              (0x4 << 15)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1		(0x0 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2		(0x1 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3		(0x2 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4		(0x3 << 21)
+
+#define DMC_MEMORY_CFG2_CLK_ASYNC		(0x0 << 0)
+#define DMC_MEMORY_CFG2_CLK_SYNC		(0x1 << 0)
+#define DMC_MEMORY_CFG2_DQM_INIT		(0x1 << 2)
+#define DMC_MEMORY_CFG2_CKE_INIT		(0x1 << 3)
+#define DMC_MEMORY_CFG2_BANK_BITS_2		(0x0 << 4)
+#define DMC_MEMORY_CFG2_BANK_BITS_3		(0x3 << 4)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_16		(0x0 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_32		(0x1 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_64		(0x2 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED	(0x3 << 6)
+
+
+
+VOID PL341DmcInit(struct pl341_dmc_config *config);
+
+
+#endif /* PL341DMC_H_ */
diff --git a/ArmPkg/Include/Drivers/PL390Gic.h b/ArmPkg/Include/Drivers/PL390Gic.h
new file mode 100644
index 0000000000..823e6c0200
--- /dev/null
+++ b/ArmPkg/Include/Drivers/PL390Gic.h
@@ -0,0 +1,120 @@
+/** @file

+*

+*  Copyright (c) 2011, ARM Limited. All rights reserved.

+*  

+*  This program and the accompanying materials                          

+*  are licensed and made available under the terms and conditions of the BSD License         

+*  which accompanies this distribution.  The full text of the license may be found at        

+*  http://opensource.org/licenses/bsd-license.php                                            

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+*

+**/

+

+#ifndef __PL390GIC_H

+#define __PL390GIC_H

+

+//

+// GIC definitions

+//

+

+// Distributor

+#define GIC_ICDDCR          0x000 // Distributor Control Register

+#define GIC_ICDICTR         0x004 // Interrupt Controller Type Register

+#define GIC_ICDIIDR         0x008 // Implementer Identification Register

+

+// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)

+#define GIC_ICDISR          0x080 // Interrupt Security Registers

+#define GIC_ICDISER         0x100 // Interrupt Set-Enable Registers

+#define GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers

+#define GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers

+#define GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers

+#define GIC_ICDABR          0x300 // Active Bit Registers

+

+// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES

+#define GIC_ICDIPR          0x400 // Interrupt Priority Registers

+

+// each reg base below repeats for VE_NUM_GIC_INTERRUPTS

+#define GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers

+#define GIC_ICDICFR         0xC00 // Interrupt Configuration Registers

+

+// just one of these

+#define GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register

+

+// Cpu interface

+#define GIC_ICCICR          0x00  // CPU Interface Control Register

+#define GIC_ICCPMR          0x04  // Interrupt Priority Mask Register

+#define GIC_ICCBPR          0x08  // Binary Point Register

+#define GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register

+#define GIC_ICCEIOR         0x10  // End Of Interrupt Register

+#define GIC_ICCRPR          0x14  // Running Priority Register

+#define GIC_ICCPIR          0x18  // Highest Pending Interrupt Register

+#define GIC_ICCABPR         0x1C  // Aliased Binary Point Register

+#define GIC_ICCIDR          0xFC  // Identification Register

+

+#define GIC_ICDSGIR_FILTER_TARGETLIST       0x0

+#define GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1

+#define GIC_ICDSGIR_FILTER_ITSELF           0x2

+

+//Bit-masks to configure the CPU Interface Control register

+#define GIC_ICCICR_ENABLE_SECURE(a)       ((a << 0) & 0x01)

+#define GIC_ICCICR_ENABLE_NS(a)           ((a << 1) & 0x02)

+#define GIC_ICCICR_ACK_CTL(a)             ((a << 2) & 0x04)

+#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)

+#define GIC_ICCICR_USE_SBPR(a)            ((a << 4) & 0x10)

+

+

+//

+// GIC SEC interfaces

+//

+VOID

+EFIAPI

+PL390GicSetupNonSecure (

+  IN  INTN          GicDistributorBase,

+  IN  INTN          GicInterruptInterfaceBase

+  );

+

+VOID

+EFIAPI

+PL390GicEnableInterruptInterface (

+  IN  INTN          GicInterruptInterfaceBase

+  );

+

+VOID

+EFIAPI

+PL390GicEnableDistributor (

+  IN  INTN          GicDistributorBase

+  );

+

+VOID

+EFIAPI

+PL390GicSendSgiTo (

+  IN  INTN          GicDistributorBase,

+  IN  INTN          TargetListFilter,

+  IN  INTN          CPUTargetList

+  );

+

+UINT32

+EFIAPI

+PL390GicAcknowledgeSgiFrom (

+  IN  INTN          GicInterruptInterfaceBase,

+  IN  INTN          CoreId

+  );

+

+UINT32

+EFIAPI

+PL390GicAcknowledgeSgi2From (

+  IN  INTN          GicInterruptInterfaceBase,

+  IN  INTN          CoreId,

+  IN  INTN          SgiId

+  );

+

+UINTN

+EFIAPI

+PL390GicSetPriorityMask (

+  IN  INTN          GicInterruptInterfaceBase,

+  IN  INTN          PriorityMask

+  );

+

+#endif