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| author | Olivier Martin <olivier.martin@arm.com> | 2014-06-03 16:39:23 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-06-03 16:39:23 +0000 |
| commit | 27331bff97f4fb36bee3aad8e010576ca641304e (patch) | |
| tree | 59cf544f153853f9b0912c5ba575e9fc52539047 /ArmPkg/Include | |
| parent | 01674afdad3460f1c1f5f7a941c4c5895c8c3f86 (diff) | |
| download | edk2-platforms-27331bff97f4fb36bee3aad8e010576ca641304e.tar.xz | |
ArmPkg: Added new ARM Processor Feature Register definitions
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include')
| -rw-r--r-- | ArmPkg/Include/Chipset/AArch64.h | 1 | ||||
| -rw-r--r-- | ArmPkg/Include/Chipset/ArmV7.h | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 3e5b55bfd7..72bde15afe 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -33,6 +33,7 @@ // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
#define AARCH64_PFR0_FP (0xF << 16)
+#define AARCH64_PFR0_GIC (0xF << 24)
// SCR - Secure Configuration Register definitions
#define SCR_NS (1 << 0)
diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h index 345554eb28..839a192516 100644 --- a/ArmPkg/Include/Chipset/ArmV7.h +++ b/ArmPkg/Include/Chipset/ArmV7.h @@ -22,6 +22,11 @@ // ARM Interrupt ID in Exception Table
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
+// ID_PFR1 - ARM Processor Feature Register 1 definitions
+#define ARM_PFR1_SEC (0xFUL << 4)
+#define ARM_PFR1_TIMER (0xFUL << 16)
+#define ARM_PFR1_GIC (0xFUL << 28)
+
// Domain Access Control Register
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
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