ArmPkg/ArmLib: Clean ArmV7Lib

- Move the non specific ArmV7 functions to ArmLib.
- Clean the ARM Platform common components to not depend on ArmV7 if not required



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 97 insertions, 126 deletions

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 5fab7eddbe..909686ce36 100644
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -1,6 +1,7 @@
 /** @file

 

   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

+  Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>

 

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

@@ -24,28 +25,6 @@
 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))

 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))

 

-// Cortex A9 feature bit definitions

-#define A9_FEATURE_PARITY  (1<<9)

-#define A9_FEATURE_AOW     (1<<8)

-#define A9_FEATURE_EXCL    (1<<7)

-#define A9_FEATURE_SMP     (1<<6)

-#define A9_FEATURE_FOZ     (1<<3)

-#define A9_FEATURE_DPREF   (1<<2)

-#define A9_FEATURE_HINT    (1<<1)

-#define A9_FEATURE_FWD     (1<<0)

-

-// SCU register offsets & masks

-#define SCU_CONTROL_OFFSET       0x0

-#define SCU_CONFIG_OFFSET        0x4

-#define SCU_INVALL_OFFSET        0xC

-#define SCU_FILT_START_OFFSET    0x40

-#define SCU_FILT_END_OFFSET      0x44

-#define SCU_SACR_OFFSET          0x50

-#define SCU_SSACR_OFFSET         0x54

-

-#define SMP_GIC_CPUIF_BASE       0x100

-#define SMP_GIC_DIST_BASE        0x1000

-

 // CPACR - Coprocessor Access Control Register definitions

 #define CPACR_CP_DENIED(cp)     0x00

 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)

@@ -71,121 +50,24 @@
 #define SCR_FW                  (1 << 4)

 #define SCR_AW                  (1 << 5)

 

-VOID

-EFIAPI

-ArmEnableSWPInstruction (

-  VOID

-  );

+// MIDR - Main ID Register definitions

+#define ARM_CPU_TYPE_MASK       0xFFF

+#define ARM_CPU_TYPE_A15        0xC0F

+#define ARM_CPU_TYPE_A9         0xC09

+#define ARM_CPU_TYPE_A5         0xC05

 

 VOID

 EFIAPI

-ArmWriteNsacr (

-  IN  UINT32   SetWayFormat

-  );

-

-VOID

-EFIAPI

-ArmWriteScr (

-  IN  UINT32   SetWayFormat

-  );

-

-VOID

-EFIAPI

-ArmWriteVMBar (

-  IN  UINT32   SetWayFormat

-  );

-

-VOID

-EFIAPI

-ArmWriteVBar (

-  IN  UINT32   SetWayFormat

-  );

-

-UINT32

-EFIAPI

-ArmReadVBar (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmWriteCPACR (

-  IN  UINT32   SetWayFormat

-  );

-

-VOID

-EFIAPI

-ArmEnableVFP (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmCallWFI (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmInvalidScu (

-  VOID

-  );

-

-UINTN

-EFIAPI

-ArmGetScuBaseAddress (

-  VOID

-  );

-

-UINT32

-EFIAPI

-ArmIsScuEnable (

-  VOID

-  );

-

-VOID

-EFIAPI

-ArmWriteAuxCr (

-  IN  UINT32    Bit

-  );

-

-UINT32

-EFIAPI

-ArmReadAuxCr (

+ArmEnableSWPInstruction (

   VOID

   );

 

-VOID

-EFIAPI

-ArmSetAuxCrBit (

-  IN  UINT32    Bits

-  );

-

-VOID

-EFIAPI

-ArmSetupSmpNonSecure (

-  IN  UINTN                     CoreId

-  );

-

 UINTN 

 EFIAPI

 ArmReadCbar (

   VOID

   );

 

-VOID

-EFIAPI

-ArmInvalidateInstructionAndDataTlb (

-  VOID

-  );

-

-

-UINTN

-EFIAPI

-ArmReadMpidr (

-  VOID

-  );

-

 UINTN

 EFIAPI

 ArmReadTpidrurw (

@@ -198,4 +80,10 @@ ArmWriteTpidrurw (
   UINTN Value

   );

 

+UINTN

+EFIAPI

+ArmReadIdPfr1 (

+  VOID

+  );

+  

 #endif // __ARM_V7_H__

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 89d915a8df..e88633e1e9 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -15,6 +15,12 @@
 #ifndef __ARM_LIB__
 #define __ARM_LIB__
 
+#ifdef ARM_CPU_ARMv6
+#include <Chipset/ARM1176JZ-S.h>
+#else
+#include <Chipset/ArmV7.h>
+#endif
+
 typedef enum {
   ARM_CACHE_TYPE_WRITE_BACK,
   ARM_CACHE_TYPE_UNKNOWN
@@ -252,6 +258,12 @@ ArmDisableCachesAndMmu (
 
 VOID
 EFIAPI
+ArmInvalidateInstructionAndDataTlb (
+  VOID
+  );
+
+VOID
+EFIAPI
 ArmEnableInterrupts (
   VOID
   );
@@ -384,6 +396,77 @@ EFIAPI
 ArmInstructionSynchronizationBarrier (
   VOID
   );
-  
+
+VOID
+EFIAPI
+ArmWriteVBar (
+  IN  UINT32   VectorBase
+  );
+
+UINT32
+EFIAPI
+ArmReadVBar (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteAuxCr (
+  IN  UINT32    Bit
+  );
+
+UINT32
+EFIAPI
+ArmReadAuxCr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmSetAuxCrBit (
+  IN  UINT32    Bits
+  );
+
+VOID
+EFIAPI
+ArmCallWFI (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmReadMpidr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteCPACR (
+  IN  UINT32   Access
+  );
+
+VOID
+EFIAPI
+ArmEnableVFP (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteNsacr (
+  IN  UINT32   SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmWriteScr (
+  IN  UINT32   SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmWriteVMBar (
+  IN  UINT32   VectorMonitorBase
+  );
 
 #endif // __ARM_LIB__