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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-05-11 10:38:47 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-05-12 13:53:08 +0200 |
| commit | cf580da1bc4c16026cb1732f741a892b2d3d3d67 (patch) | |
| tree | d4b3b771dbfb0914e8af897c27b3c8668084e185 /ArmPkg/Library/ArmCacheMaintenanceLib | |
| parent | 14b2ebc30c8bc98f668fa78171b659e2cdc33aa5 (diff) | |
| download | edk2-platforms-cf580da1bc4c16026cb1732f741a892b2d3d3d67.tar.xz | |
ArmPkg/ArmLib: don't invalidate entire I-cache on range operation
Instead of cleaning the data cache to the PoU by virtual address and
subsequently invalidating the entire I-cache, invalidate only the
range that we just cleaned. This way, we don't invalidate other
cachelines unnecessarily.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPkg/Library/ArmCacheMaintenanceLib')
| -rw-r--r-- | ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index 1045f9068f..0759e38cd4 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -17,15 +17,16 @@ #include <Library/DebugLib.h>
#include <Library/PcdLib.h>
+STATIC
VOID
CacheRangeOperation (
IN VOID *Start,
IN UINTN Length,
- IN LINE_OPERATION LineOperation
+ IN LINE_OPERATION LineOperation,
+ IN UINTN LineLength
)
{
- UINTN ArmCacheLineLength = ArmDataCacheLineLength();
- UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
+ UINTN ArmCacheLineAlignmentMask = LineLength - 1;
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
@@ -34,7 +35,7 @@ CacheRangeOperation ( // Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
- AlignedAddress += ArmCacheLineLength;
+ AlignedAddress += LineLength;
}
ArmDataSynchronizationBarrier ();
}
@@ -64,8 +65,14 @@ InvalidateInstructionCacheRange ( IN UINTN Length
)
{
- CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA);
- ArmInvalidateInstructionCache ();
+ CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,
+ ArmDataCacheLineLength ());
+ CacheRangeOperation (Address, Length,
+ ArmInvalidateInstructionCacheEntryToPoUByMVA,
+ ArmInstructionCacheLineLength ());
+
+ ArmInstructionSynchronizationBarrier ();
+
return Address;
}
@@ -85,7 +92,8 @@ WriteBackInvalidateDataCacheRange ( IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);
+ CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,
+ ArmDataCacheLineLength ());
return Address;
}
@@ -105,7 +113,8 @@ WriteBackDataCacheRange ( IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);
+ CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,
+ ArmDataCacheLineLength ());
return Address;
}
@@ -116,6 +125,7 @@ InvalidateDataCacheRange ( IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);
+ CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,
+ ArmDataCacheLineLength ());
return Address;
}
|