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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-07-28 20:44:58 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-07-28 20:44:58 +0000 |
| commit | e9e9c7e8a4a987f9e68c016514aa8b60570a6450 (patch) | |
| tree | c02093402511e807d1e94a6e5d3d55dd579b6e91 /ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c | |
| parent | 8d13298b8008ff62e107deb2a293ea267943a977 (diff) | |
| download | edk2-platforms-e9e9c7e8a4a987f9e68c016514aa8b60570a6450.tar.xz | |
ArmPkg: copy ArmGicArchLib to ArmGicArchSecLib
Clone ArmGicArchLib into a SEC phase specific ArmGicArchSecLib
so that we can modify the former in a subsequent patch to cache
the GIC revision in a global variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18099 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c')
| -rw-r--r-- | ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c new file mode 100644 index 0000000000..f256de7046 --- /dev/null +++ b/ArmPkg/Library/ArmGicArchSecLib/Arm/ArmGicArchLib.c @@ -0,0 +1,51 @@ +/** @file
+*
+* Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made available
+* under the terms and conditions of the BSD License which accompanies this
+* distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmGicLib.h>
+
+ARM_GIC_ARCH_REVISION
+EFIAPI
+ArmGicGetSupportedArchRevision (
+ VOID
+ )
+{
+ UINT32 IccSre;
+
+ // Ideally we would like to use the GICC IIDR Architecture version here, but
+ // this does not seem to be very reliable as the implementation could easily
+ // get it wrong. It is more reliable to check if the GICv3 System Register
+ // feature is implemented on the CPU. This is also convenient as our GICv3
+ // driver requires SRE. If only Memory mapped access is available we try to
+ // drive the GIC as a v2.
+ if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
+ // Make sure System Register access is enabled (SRE). This depends on the
+ // higher privilege level giving us permission, otherwise we will either
+ // cause an exception here, or the write doesn't stick in which case we need
+ // to fall back to the GICv2 MMIO interface.
+ // Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
+ // at the same exception level.
+ // It is the OS responsibility to set this bit.
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ if (!(IccSre & ICC_SRE_EL2_SRE)) {
+ ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
+ IccSre = ArmGicV3GetControlSystemRegisterEnable ();
+ }
+ if (IccSre & ICC_SRE_EL2_SRE) {
+ return ARM_GIC_ARCH_REVISION_3;
+ }
+ }
+
+ return ARM_GIC_ARCH_REVISION_2;
+}
|