diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-09 13:26:32 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-09 13:26:32 +0000 |
| commit | f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b (patch) | |
| tree | 55a182b6e3cc880ceb2ebdf9c0df3e2a035b3411 /ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | |
| parent | acdb6dc8b739ccddd8425e609b68871151c5b94e (diff) | |
| download | edk2-platforms-f97ab1bbf4c4512e1aabd149527c1aa4d5b0c03b.tar.xz | |
ArmPkg/ArmLib: remove CCSIDR based cache info routines
The ARM architecture does not allow the actual geometries of the caches
to be inferred from the CCSIDR cache info system register, since the
geometry it reports is intended for performing cache maintenance by
set/way and nothing else. Since the ArmLib cache info routines are
based solely on CCSIDR contents, they should not be used.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c')
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 141 |
1 files changed, 0 insertions, 141 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c index f795a2f896..4bea20356f 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -21,86 +21,6 @@ #include "AArch64Lib.h"
#include "ArmLibPrivate.h"
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- )
-{
- return ARM_CACHE_TYPE_WRITE_BACK;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- )
-{
- UINT32 CLIDR = ReadCLIDR ();
-
- return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- )
-{
- UINT32 CLIDR = ReadCLIDR ();
-
- if ((CLIDR & 0x2) == 0x2) {
- // Instruction cache exists
- return TRUE;
- }
- if ((CLIDR & 0x7) == 0x4) {
- // Unified cache
- return TRUE;
- }
-
- return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
- )
-{
- UINT32 NumSets;
- UINT32 Associativity;
- UINT32 LineSize;
- UINT32 CCSIDR = ReadCCSIDR (0);
-
- LineSize = (1 << ((CCSIDR & 0x7) + 2));
- Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
- NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
-
- // LineSize is in words (4 byte chunks)
- return NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (0);
-
- return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-
-UINTN
-ArmDataCacheSets (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (0);
-
- return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
UINTN
EFIAPI
ArmDataCacheLineLength (
@@ -113,67 +33,6 @@ ArmDataCacheLineLength ( return (1 << (CCSIDR + 2)) * 4;
}
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- )
-{
- UINT32 CLIDR = ReadCLIDR ();
-
- if ((CLIDR & 1) == 1) {
- // Instruction cache exists
- return TRUE;
- }
- if ((CLIDR & 0x7) == 0x4) {
- // Unified cache
- return TRUE;
- }
-
- return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- )
-{
- UINT32 NumSets;
- UINT32 Associativity;
- UINT32 LineSize;
- UINT32 CCSIDR = ReadCCSIDR (1);
-
- LineSize = (1 << ((CCSIDR & 0x7) + 2));
- Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
- NumSets = ((CCSIDR >> 13) & 0x7fff) + 1;
-
- // LineSize is in words (4 byte chunks)
- return NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (1);
-
- return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSets (
- VOID
- )
-{
- UINT32 CCSIDR = ReadCCSIDR (1);
-
- return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
UINTN
EFIAPI
ArmInstructionCacheLineLength (
|