ArmPkg/ArmLib: switch to ASM_FUNC() asm macro

Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

3 files changed, 75 insertions, 156 deletions

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S
index 3944d8bcb4..59e0bc9a07 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S
@@ -1,6 +1,7 @@
 #------------------------------------------------------------------------------

 #

 # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.

+# Copyright (c) 2016, Linaro Limited. All rights reserved.

 #

 # This program and the accompanying materials

 # are licensed and made available under the terms and conditions of the BSD License

@@ -12,127 +13,105 @@
 #

 #------------------------------------------------------------------------------

 

-.text

-.align 2

-

-GCC_ASM_EXPORT(ArmReadCntFrq)

-GCC_ASM_EXPORT(ArmWriteCntFrq)

-GCC_ASM_EXPORT(ArmReadCntPct)

-GCC_ASM_EXPORT(ArmReadCntkCtl)

-GCC_ASM_EXPORT(ArmWriteCntkCtl)

-GCC_ASM_EXPORT(ArmReadCntpTval)

-GCC_ASM_EXPORT(ArmWriteCntpTval)

-GCC_ASM_EXPORT(ArmReadCntpCtl)

-GCC_ASM_EXPORT(ArmWriteCntpCtl)

-GCC_ASM_EXPORT(ArmReadCntvTval)

-GCC_ASM_EXPORT(ArmWriteCntvTval)

-GCC_ASM_EXPORT(ArmReadCntvCtl)

-GCC_ASM_EXPORT(ArmWriteCntvCtl)

-GCC_ASM_EXPORT(ArmReadCntvCt)

-GCC_ASM_EXPORT(ArmReadCntpCval)

-GCC_ASM_EXPORT(ArmWriteCntpCval)

-GCC_ASM_EXPORT(ArmReadCntvCval)

-GCC_ASM_EXPORT(ArmWriteCntvCval)

-GCC_ASM_EXPORT(ArmReadCntvOff)

-GCC_ASM_EXPORT(ArmWriteCntvOff)

-

-ASM_PFX(ArmReadCntFrq):

+#include <AsmMacroIoLibV8.h>

+

+ASM_FUNC(ArmReadCntFrq)

   mrs   x0, cntfrq_el0           // Read CNTFRQ

   ret

 

 

 # NOTE - Can only write while at highest implemented EL level (EL3 on model). Else ReadOnly (EL2, EL1, EL0)

-ASM_PFX(ArmWriteCntFrq):

+ASM_FUNC(ArmWriteCntFrq)

   msr   cntfrq_el0, x0           // Write to CNTFRQ

   ret

 

 

-ASM_PFX(ArmReadCntPct):

+ASM_FUNC(ArmReadCntPct)

   mrs   x0, cntpct_el0           // Read CNTPCT (Physical counter register)

   ret

 

 

-ASM_PFX(ArmReadCntkCtl):

+ASM_FUNC(ArmReadCntkCtl)

   mrs   x0, cntkctl_el1          // Read CNTK_CTL (Timer PL1 Control Register)

   ret

 

 

-ASM_PFX(ArmWriteCntkCtl):

+ASM_FUNC(ArmWriteCntkCtl)

   msr   cntkctl_el1, x0          // Write to CNTK_CTL (Timer PL1 Control Register)

   ret

 

 

-ASM_PFX(ArmReadCntpTval):

+ASM_FUNC(ArmReadCntpTval)

   mrs   x0, cntp_tval_el0        // Read CNTP_TVAL (PL1 physical timer value register)

   ret

 

 

-ASM_PFX(ArmWriteCntpTval):

+ASM_FUNC(ArmWriteCntpTval)

   msr   cntp_tval_el0, x0        // Write to CNTP_TVAL (PL1 physical timer value register)

   ret

 

 

-ASM_PFX(ArmReadCntpCtl):

+ASM_FUNC(ArmReadCntpCtl)

   mrs   x0, cntp_ctl_el0         // Read CNTP_CTL (PL1 Physical Timer Control Register)

   ret

 

 

-ASM_PFX(ArmWriteCntpCtl):

+ASM_FUNC(ArmWriteCntpCtl)

   msr   cntp_ctl_el0, x0         // Write to  CNTP_CTL (PL1 Physical Timer Control Register)

   ret

 

 

-ASM_PFX(ArmReadCntvTval):

+ASM_FUNC(ArmReadCntvTval)

   mrs   x0, cntv_tval_el0        // Read CNTV_TVAL (Virtual Timer Value register)

   ret

 

 

-ASM_PFX(ArmWriteCntvTval):

+ASM_FUNC(ArmWriteCntvTval)

   msr   cntv_tval_el0, x0        // Write to CNTV_TVAL (Virtual Timer Value register)

   ret

 

 

-ASM_PFX(ArmReadCntvCtl):

+ASM_FUNC(ArmReadCntvCtl)

   mrs   x0, cntv_ctl_el0         // Read CNTV_CTL (Virtual Timer Control Register)

   ret

 

 

-ASM_PFX(ArmWriteCntvCtl):

+ASM_FUNC(ArmWriteCntvCtl)

   msr   cntv_ctl_el0, x0         // Write to CNTV_CTL (Virtual Timer Control Register)

   ret

 

 

-ASM_PFX(ArmReadCntvCt):

+ASM_FUNC(ArmReadCntvCt)

   mrs  x0, cntvct_el0            // Read CNTVCT  (Virtual Count Register)

   ret

 

 

-ASM_PFX(ArmReadCntpCval):

+ASM_FUNC(ArmReadCntpCval)

   mrs   x0, cntp_cval_el0        // Read CNTP_CTVAL (Physical Timer Compare Value Register)

   ret

 

 

-ASM_PFX(ArmWriteCntpCval):

+ASM_FUNC(ArmWriteCntpCval)

   msr   cntp_cval_el0, x0        // Write to CNTP_CTVAL (Physical Timer Compare Value Register)

   ret

 

 

-ASM_PFX(ArmReadCntvCval):

+ASM_FUNC(ArmReadCntvCval)

   mrs   x0, cntv_cval_el0        // Read CNTV_CTVAL (Virtual Timer Compare Value Register)

   ret

 

 

-ASM_PFX(ArmWriteCntvCval):

+ASM_FUNC(ArmWriteCntvCval)

   msr   cntv_cval_el0, x0        // write to  CNTV_CTVAL (Virtual Timer Compare Value Register)

   ret

 

 

-ASM_PFX(ArmReadCntvOff):

+ASM_FUNC(ArmReadCntvOff)

   mrs   x0, cntvoff_el2          // Read CNTVOFF (virtual Offset register)

   ret

 

 

-ASM_PFX(ArmWriteCntvOff):

+ASM_FUNC(ArmWriteCntvOff)

   msr   cntvoff_el2, x0          // Write to CNTVOFF (Virtual Offset register)

   ret

 

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 5cef98fd42..5cee7c1519 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -2,6 +2,7 @@
 #

 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>

 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.

+# Copyright (c) 2016, Linaro Limited. All rights reserved.

 #

 # This program and the accompanying materials

 # are licensed and made available under the terms and conditions of the BSD License

@@ -16,50 +17,6 @@
 #include <Chipset/AArch64.h>

 #include <AsmMacroIoLibV8.h>

 

-.text

-.align 3

-

-GCC_ASM_EXPORT (ArmInvalidateInstructionCache)

-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)

-GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)

-GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)

-GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)

-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)

-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)

-GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)

-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)

-GCC_ASM_EXPORT (ArmEnableMmu)

-GCC_ASM_EXPORT (ArmDisableMmu)

-GCC_ASM_EXPORT (ArmDisableCachesAndMmu)

-GCC_ASM_EXPORT (ArmMmuEnabled)

-GCC_ASM_EXPORT (ArmEnableDataCache)

-GCC_ASM_EXPORT (ArmDisableDataCache)

-GCC_ASM_EXPORT (ArmEnableInstructionCache)

-GCC_ASM_EXPORT (ArmDisableInstructionCache)

-GCC_ASM_EXPORT (ArmDisableAlignmentCheck)

-GCC_ASM_EXPORT (ArmEnableAlignmentCheck)

-GCC_ASM_EXPORT (ArmEnableBranchPrediction)

-GCC_ASM_EXPORT (ArmDisableBranchPrediction)

-GCC_ASM_EXPORT (AArch64AllDataCachesOperation)

-GCC_ASM_EXPORT (ArmDataMemoryBarrier)

-GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)

-GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)

-GCC_ASM_EXPORT (ArmWriteVBar)

-GCC_ASM_EXPORT (ArmReadVBar)

-GCC_ASM_EXPORT (ArmEnableVFP)

-GCC_ASM_EXPORT (ArmCallWFI)

-GCC_ASM_EXPORT (ArmReadMpidr)

-GCC_ASM_EXPORT (ArmReadTpidrurw)

-GCC_ASM_EXPORT (ArmWriteTpidrurw)

-GCC_ASM_EXPORT (ArmIsArchTimerImplemented)

-GCC_ASM_EXPORT (ArmReadIdPfr0)

-GCC_ASM_EXPORT (ArmReadIdPfr1)

-GCC_ASM_EXPORT (ArmWriteHcr)

-GCC_ASM_EXPORT (ArmReadHcr)

-GCC_ASM_EXPORT (ArmReadCurrentEL)

-GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntry)

-GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize)

-

 .set CTRL_M_BIT,      (1 << 0)

 .set CTRL_A_BIT,      (1 << 1)

 .set CTRL_C_BIT,      (1 << 2)

@@ -67,53 +24,53 @@ GCC_ASM_EXPORT (ArmReplaceLiveTranslationEntrySize)
 .set CTRL_V_BIT,      (1 << 12)

 .set CPACR_VFP_BITS,  (3 << 20)

 

-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):

+ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)

   dc      ivac, x0    // Invalidate single data cache line

   ret

 

 

-ASM_PFX(ArmCleanDataCacheEntryByMVA):

+ASM_FUNC(ArmCleanDataCacheEntryByMVA)

   dc      cvac, x0    // Clean single data cache line

   ret

 

 

-ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):

+ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)

   dc      cvau, x0    // Clean single data cache line to PoU

   ret

 

-ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):

+ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)

   ic      ivau, x0    // Invalidate single instruction cache line to PoU

   ret

 

 

-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):

+ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)

   dc      civac, x0   // Clean and invalidate single data cache line

   ret

 

 

-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):

+ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)

   dc      isw, x0     // Invalidate this line

   ret

 

 

-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):

+ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)

   dc      cisw, x0    // Clean and Invalidate this line

   ret

 

 

-ASM_PFX(ArmCleanDataCacheEntryBySetWay):

+ASM_FUNC(ArmCleanDataCacheEntryBySetWay)

   dc      csw, x0     // Clean this line

   ret

 

 

-ASM_PFX(ArmInvalidateInstructionCache):

+ASM_FUNC(ArmInvalidateInstructionCache)

   ic      iallu       // Invalidate entire instruction cache

   dsb     sy

   isb

   ret

 

 

-ASM_PFX(ArmEnableMmu):

+ASM_FUNC(ArmEnableMmu)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1       // Read System control register EL1

    b       4f

@@ -140,7 +97,7 @@ ASM_PFX(ArmEnableMmu):
    ret

 

 

-ASM_PFX(ArmDisableMmu):

+ASM_FUNC(ArmDisableMmu)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Read System Control Register EL1

    b       4f

@@ -162,7 +119,7 @@ ASM_PFX(ArmDisableMmu):
    ret

 

 

-ASM_PFX(ArmDisableCachesAndMmu):

+ASM_FUNC(ArmDisableCachesAndMmu)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -182,7 +139,7 @@ ASM_PFX(ArmDisableCachesAndMmu):
    ret

 

 

-ASM_PFX(ArmMmuEnabled):

+ASM_FUNC(ArmMmuEnabled)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -193,7 +150,7 @@ ASM_PFX(ArmMmuEnabled):
    ret

 

 

-ASM_PFX(ArmEnableDataCache):

+ASM_FUNC(ArmEnableDataCache)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -212,7 +169,7 @@ ASM_PFX(ArmEnableDataCache):
    ret

 

 

-ASM_PFX(ArmDisableDataCache):

+ASM_FUNC(ArmDisableDataCache)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -231,7 +188,7 @@ ASM_PFX(ArmDisableDataCache):
    ret

 

 

-ASM_PFX(ArmEnableInstructionCache):

+ASM_FUNC(ArmEnableInstructionCache)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -250,7 +207,7 @@ ASM_PFX(ArmEnableInstructionCache):
    ret

 

 

-ASM_PFX(ArmDisableInstructionCache):

+ASM_FUNC(ArmDisableInstructionCache)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -269,7 +226,7 @@ ASM_PFX(ArmDisableInstructionCache):
    ret

 

 

-ASM_PFX(ArmEnableAlignmentCheck):

+ASM_FUNC(ArmEnableAlignmentCheck)

    EL1_OR_EL2(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       3f

@@ -284,7 +241,7 @@ ASM_PFX(ArmEnableAlignmentCheck):
    ret

 

 

-ASM_PFX(ArmDisableAlignmentCheck):

+ASM_FUNC(ArmDisableAlignmentCheck)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs     x0, sctlr_el1        // Get control register EL1

    b       4f

@@ -304,16 +261,16 @@ ASM_PFX(ArmDisableAlignmentCheck):
 

 

 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now

-ASM_PFX(ArmEnableBranchPrediction):

+ASM_FUNC(ArmEnableBranchPrediction)

   ret

 

 

 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.

-ASM_PFX(ArmDisableBranchPrediction):

+ASM_FUNC(ArmDisableBranchPrediction)

   ret

 

 

-ASM_PFX(AArch64AllDataCachesOperation):

+ASM_FUNC(AArch64AllDataCachesOperation)

 // We can use regs 0-7 and 9-15 without having to save/restore.

 // Save our link register on the stack. - The stack must always be quad-word aligned

   str   x30, [sp, #-16]!

@@ -371,22 +328,22 @@ L_Finished:
   ret

 

 

-ASM_PFX(ArmDataMemoryBarrier):

+ASM_FUNC(ArmDataMemoryBarrier)

   dmb   sy

   ret

 

 

-ASM_PFX(ArmDataSynchronizationBarrier):

+ASM_FUNC(ArmDataSynchronizationBarrier)

   dsb   sy

   ret

 

 

-ASM_PFX(ArmInstructionSynchronizationBarrier):

+ASM_FUNC(ArmInstructionSynchronizationBarrier)

   isb

   ret

 

 

-ASM_PFX(ArmWriteVBar):

+ASM_FUNC(ArmWriteVBar)

    EL1_OR_EL2_OR_EL3(x1)

 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register

    b     4f

@@ -396,7 +353,7 @@ ASM_PFX(ArmWriteVBar):
 4: isb

    ret

 

-ASM_PFX(ArmReadVBar):

+ASM_FUNC(ArmReadVBar)

    EL1_OR_EL2_OR_EL3(x1)

 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register

    ret

@@ -406,7 +363,7 @@ ASM_PFX(ArmReadVBar):
    ret

 

 

-ASM_PFX(ArmEnableVFP):

+ASM_FUNC(ArmEnableVFP)

   // Check whether floating-point is implemented in the processor.

   mov   x1, x30                 // Save LR

   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)

@@ -432,35 +389,35 @@ ASM_PFX(ArmEnableVFP):
 4:ret

 

 

-ASM_PFX(ArmCallWFI):

+ASM_FUNC(ArmCallWFI)

   wfi

   ret

 

 

-ASM_PFX(ArmReadMpidr):

+ASM_FUNC(ArmReadMpidr)

   mrs   x0, mpidr_el1           // read EL1 MPIDR

   ret

 

 

 // Keep old function names for C compatibilty for now. Change later?

-ASM_PFX(ArmReadTpidrurw):

+ASM_FUNC(ArmReadTpidrurw)

   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)

   ret

 

 

 // Keep old function names for C compatibilty for now. Change later?

-ASM_PFX(ArmWriteTpidrurw):

+ASM_FUNC(ArmWriteTpidrurw)

   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)

   ret

 

 

 // Arch timers are mandatory on AArch64

-ASM_PFX(ArmIsArchTimerImplemented):

+ASM_FUNC(ArmIsArchTimerImplemented)

   mov   x0, #1

   ret

 

 

-ASM_PFX(ArmReadIdPfr0):

+ASM_FUNC(ArmReadIdPfr0)

   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register

   ret

 

@@ -469,22 +426,22 @@ ASM_PFX(ArmReadIdPfr0):
 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.

 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c

 //    Not defined yet, but stick in here for now, should read all zeros.

-ASM_PFX(ArmReadIdPfr1):

+ASM_FUNC(ArmReadIdPfr1)

   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register

   ret

 

 // VOID ArmWriteHcr(UINTN Hcr)

-ASM_PFX(ArmWriteHcr):

+ASM_FUNC(ArmWriteHcr)

   msr   hcr_el2, x0        // Write the passed HCR value

   ret

 

 // UINTN ArmReadHcr(VOID)

-ASM_PFX(ArmReadHcr):

+ASM_FUNC(ArmReadHcr)

   mrs   x0, hcr_el2

   ret

 

 // UINTN ArmReadCurrentEL(VOID)

-ASM_PFX(ArmReadCurrentEL):

+ASM_FUNC(ArmReadCurrentEL)

   mrs   x0, CurrentEL

   ret

 

diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
index 341bbce76c..221dfc499a 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
@@ -2,6 +2,7 @@
 #

 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.

+# Copyright (c) 2016, Linaro Limited. All rights reserved.

 #

 # This program and the accompanying materials

 # are licensed and made available under the terms and conditions of the BSD License

@@ -15,24 +16,6 @@
 

 #include <AsmMacroIoLibV8.h>

 

-.text

-.align 3

-

-GCC_ASM_EXPORT (ArmIsMpCore)

-GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)

-GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)

-GCC_ASM_EXPORT (ArmEnableIrq)

-GCC_ASM_EXPORT (ArmDisableIrq)

-GCC_ASM_EXPORT (ArmEnableFiq)

-GCC_ASM_EXPORT (ArmDisableFiq)

-GCC_ASM_EXPORT (ArmEnableInterrupts)

-GCC_ASM_EXPORT (ArmDisableInterrupts)

-GCC_ASM_EXPORT (ArmDisableAllExceptions)

-GCC_ASM_EXPORT (ReadCCSIDR)

-GCC_ASM_EXPORT (ReadCLIDR)

-

-#------------------------------------------------------------------------------

-

 .set MPIDR_U_BIT,    (30)

 .set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)

 

@@ -45,7 +28,7 @@ GCC_ASM_EXPORT (ReadCLIDR)
 .set DAIF_WR_ALL,       (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)

 

 

-ASM_PFX(ArmIsMpCore):

+ASM_FUNC(ArmIsMpCore)

   mrs   x0, mpidr_el1         // Read EL1 Mutliprocessor Affinty Reg (MPIDR)

   and   x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system

   lsr   x0, x0, #MPIDR_U_BIT

@@ -53,55 +36,55 @@ ASM_PFX(ArmIsMpCore):
   ret

 

 

-ASM_PFX(ArmEnableAsynchronousAbort):

+ASM_FUNC(ArmEnableAsynchronousAbort)

   msr   daifclr, #DAIF_WR_ABORT_BIT

   isb

   ret

 

 

-ASM_PFX(ArmDisableAsynchronousAbort):

+ASM_FUNC(ArmDisableAsynchronousAbort)

   msr   daifset, #DAIF_WR_ABORT_BIT

   isb

   ret

 

 

-ASM_PFX(ArmEnableIrq):

+ASM_FUNC(ArmEnableIrq)

   msr   daifclr, #DAIF_WR_IRQ_BIT

   isb

   ret

 

 

-ASM_PFX(ArmDisableIrq):

+ASM_FUNC(ArmDisableIrq)

   msr   daifset, #DAIF_WR_IRQ_BIT

   isb

   ret

 

 

-ASM_PFX(ArmEnableFiq):

+ASM_FUNC(ArmEnableFiq)

   msr   daifclr, #DAIF_WR_FIQ_BIT

   isb

   ret

 

 

-ASM_PFX(ArmDisableFiq):

+ASM_FUNC(ArmDisableFiq)

   msr   daifset, #DAIF_WR_FIQ_BIT

   isb

   ret

 

 

-ASM_PFX(ArmEnableInterrupts):

+ASM_FUNC(ArmEnableInterrupts)

   msr   daifclr, #DAIF_WR_INT_BITS

   isb

   ret

 

 

-ASM_PFX(ArmDisableInterrupts):

+ASM_FUNC(ArmDisableInterrupts)

   msr   daifset, #DAIF_WR_INT_BITS

   isb

   ret

 

 

-ASM_PFX(ArmDisableAllExceptions):

+ASM_FUNC(ArmDisableAllExceptions)

   msr   daifset, #DAIF_WR_ALL

   isb

   ret

@@ -111,7 +94,7 @@ ASM_PFX(ArmDisableAllExceptions):
 // ReadCCSIDR (

 //   IN UINT32 CSSELR

 //   )

-ASM_PFX(ReadCCSIDR):

+ASM_FUNC(ReadCCSIDR)

   msr   csselr_el1, x0        // Write Cache Size Selection Register (CSSELR)

   isb

   mrs   x0, ccsidr_el1        // Read current Cache Size ID Register (CCSIDR)

@@ -122,7 +105,7 @@ ASM_PFX(ReadCCSIDR):
 // ReadCLIDR (

 //   IN UINT32 CSSELR

 //   )

-ASM_PFX(ReadCLIDR):

+ASM_FUNC(ReadCLIDR)

   mrs   x0, clidr_el1         // Read Cache Level ID Register

   ret