Adding support for BeagleBoard.

ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers.
EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell.
BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine).


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9518 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 444 insertions, 0 deletions

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
new file mode 100644
index 0000000000..8042e4dd31
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
@@ -0,0 +1,32 @@
+#%HEADER%

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = Arm11ArmLib

+  FILE_GUID                      = 00586300-0E06-4790-AC44-86C56ACBB942

+  MODULE_TYPE                    = DXE_DRIVER

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = ArmLib

+

+[Sources.common]

+  ../Common/ArmLibSupport.S    | GCC

+  ../Common/ArmLibSupport.asm  | RVCT

+  ../Common/ArmLib.c

+  

+  Arm11Support.S    | GCC

+  Arm11Support.asm  | RVCT

+  

+  Arm11Lib.c

+  ../Arm9/Arm9CacheInformation.c

+

+[Packages]

+  ArmPkg/ArmPkg.dec

+  MdePkg/MdePkg.dec

+

+[LibraryClasses]

+  MemoryAllocationLib

+  

+[Protocols]

+  gEfiCpuArchProtocolGuid

+

+[FixedPcd]

+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
new file mode 100644
index 0000000000..040179e445
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
@@ -0,0 +1,32 @@
+#%HEADER%

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = Arm11ArmLib

+  FILE_GUID                      = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f

+  MODULE_TYPE                    = DXE_DRIVER

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = ArmLib

+

+[Sources.common]

+  ../Common/ArmLibSupport.S    | GCC

+  ../Common/ArmLibSupport.asm  | RVCT

+  ../Common/ArmLib.c

+  

+  Arm11Support.S    | GCC

+  Arm11Support.asm  | RVCT

+  

+  Arm11Lib.c

+  ../Arm9/Arm9CacheInformation.c

+

+[Packages]

+  ArmPkg/ArmPkg.dec

+  MdePkg/MdePkg.dec

+

+[LibraryClasses]

+  PrePiLib

+  

+[Protocols]

+  gEfiCpuArchProtocolGuid

+

+[FixedPcd]

+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
new file mode 100644
index 0000000000..3736904954
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
@@ -0,0 +1,118 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Chipset/ARM1176JZ-S.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+VOID
+FillTranslationTable (
+  IN  UINT32                        *TranslationTable,
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
+  )
+{
+  UINT32  *Entry;
+  UINTN   Sections;
+  UINTN   Index;
+  UINT32  Attributes;
+  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
+  
+  switch (MemoryRegion->Attributes) {
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+    default:
+      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
+      break;
+  }
+  
+  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+  Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
+  
+  for (Index = 0; Index < Sections; Index++)
+  {
+    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+  }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT UINTN                         *TranslationTableSize  OPTIONAL
+  )
+{
+  VOID  *TranslationTable;
+
+  // Allocate pages for translation table.
+  TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+  if (TranslationTableBase != NULL) {
+    *TranslationTableBase = TranslationTable;
+  }
+  
+  if (TranslationTableBase != NULL) {
+    *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+  }
+
+  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+  ArmInvalidateTlb();
+
+  ArmDisableDataCache();
+  ArmDisableInstructionCache();
+  ArmDisableMmu();
+
+  // Make sure nothing sneaked into the cache
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+
+  while (MemoryTable->Length != 0) {
+    FillTranslationTable(TranslationTable, MemoryTable);
+    MemoryTable++;
+  }
+
+  ArmSetTranslationTableBaseAddress(TranslationTable);
+    
+  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+                            DOMAIN_ACCESS_CONTROL_NONE(14) |
+                            DOMAIN_ACCESS_CONTROL_NONE(13) |
+                            DOMAIN_ACCESS_CONTROL_NONE(12) |
+                            DOMAIN_ACCESS_CONTROL_NONE(11) |
+                            DOMAIN_ACCESS_CONTROL_NONE(10) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 9) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 8) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 7) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 6) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 5) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 4) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 3) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 2) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 1) |
+                            DOMAIN_ACCESS_CONTROL_MANAGER(0));
+    
+  ArmEnableInstructionCache();
+  ArmEnableDataCache();
+  ArmEnableMmu();  
+}
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
new file mode 100644
index 0000000000..eec8f20b4e
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
@@ -0,0 +1,129 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmCleanInvalidateDataCache)
+.globl ASM_PFX(ArmCleanDataCache)
+.globl ASM_PFX(ArmInvalidateDataCache)
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line                                           
+  bx      lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
+  bx      lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
+  bx      lr
+
+
+ASM_PFX(ArmCleanDataCache):
+  mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
+  bx      lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCache):
+  mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
+  bx      lr
+
+
+ASM_PFX(ArmInvalidateDataCache):
+  mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
+  bx      lr
+
+
+ASM_PFX(ArmInvalidateInstructionCache):
+  mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
+  bx      lr
+
+ASM_PFX(ArmEnableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ASM_PFX(ArmDisableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
+  bx      LR
+
+ASM_PFX(ArmEnableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  orr     R0,R0,R1              @Set C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+    
+ASM_PFX(ArmDisableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  bic     R0,R0,R1              @Clear C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmEnableInstructionCache):
+  ldr     R1,=IC_ON
+  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
+  orr     R0,R0,R1             @Set I bit
+  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
+  bx      LR
+  
+ASM_PFX(ArmDisableInstructionCache):
+  ldr     R1,=IC_ON
+  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
+  bic     R0,R0,R1             @Clear I bit.
+  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+  mrc     p15, 0, r0, c1, c0, 0
+  orr     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+  mrc     p15, 0, r0, c1, c0, 0
+  bic     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
new file mode 100644
index 0000000000..e0be8f0c07
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
@@ -0,0 +1,133 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+    EXPORT  ArmCleanInvalidateDataCache
+    EXPORT  ArmCleanDataCache
+    EXPORT  ArmInvalidateDataCache
+    EXPORT  ArmInvalidateInstructionCache
+    EXPORT  ArmInvalidateDataCacheEntryByMVA
+    EXPORT  ArmCleanDataCacheEntryByMVA
+    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
+    EXPORT  ArmEnableMmu
+    EXPORT  ArmDisableMmu
+    EXPORT  ArmEnableDataCache
+    EXPORT  ArmDisableDataCache
+    EXPORT  ArmEnableInstructionCache
+    EXPORT  ArmDisableInstructionCache
+    EXPORT  ArmEnableBranchPrediction
+    EXPORT  ArmDisableBranchPrediction
+
+
+DC_ON       EQU     ( 0x1:SHL:2 )
+IC_ON       EQU     ( 0x1:SHL:12 )
+XP_ON       EQU     ( 0x1:SHL:23 )
+
+
+    AREA    ArmCacheLib, CODE, READONLY
+    PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
+  bx      lr
+
+
+ArmCleanDataCacheEntryByMVA
+  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  bx      lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
+  bx      lr
+
+
+ArmCleanDataCache
+  mcr     p15, 0, r0, c7, c10, 0  ; clean entire data cache
+  bx      lr
+
+
+ArmCleanInvalidateDataCache
+  mcr     p15, 0, r0, c7, c14, 0  ; clean and invalidate entire data cache
+  bx      lr
+
+
+ArmInvalidateDataCache
+  mcr     p15, 0, r0, c7, c6, 0  ; invalidate entire data cache
+  bx      lr
+
+
+ArmInvalidateInstructionCache
+  mcr     p15, 0, r0, c7, c5, 0  ;invalidate entire instruction cache
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4       ;Flush Prefetch buffer
+  bx      lr
+
+ArmEnableMmu
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ArmDisableMmu
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      ;Flush Prefetch buffer
+  bx      LR
+
+ArmEnableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  ORR     R0,R0,R1              ;Set C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+    
+ArmDisableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  BIC     R0,R0,R1              ;Clear C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+
+ArmEnableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  ORR     R0,R0,R1             ;Set I bit
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+  
+ArmDisableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  BIC     R0,R0,R1             ;Clear I bit.
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+
+ArmEnableBranchPrediction
+  mrc     p15, 0, r0, c1, c0, 0
+  orr     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ArmDisableBranchPrediction
+  mrc     p15, 0, r0, c1, c0, 0
+  bic     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+    END