diff options
| author | Ronald Cron <ronald.cron@arm.com> | 2014-08-19 13:29:52 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-19 13:29:52 +0000 |
| commit | 3402aac7d985bf8a9f9d3c639f3fe93609380513 (patch) | |
| tree | 67b11334dc45181581aaaac236243fe72c7f614c /ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c | |
| parent | 62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 (diff) | |
| download | edk2-platforms-3402aac7d985bf8a9f9d3c639f3fe93609380513.tar.xz | |
ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c index 19da4db258..f0b5060249 100644 --- a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c +++ b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c @@ -56,7 +56,7 @@ ArmDataCachePresent ( default: return FALSE;
}
}
-
+
UINTN
EFIAPI
ArmDataCacheSize (
@@ -65,16 +65,16 @@ ArmDataCacheSize ( {
switch (DATA_CACHE_SIZE (ArmCacheInfo ()))
{
- case CACHE_SIZE_4_KB: return 4 * 1024;
+ case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_8_KB: return 8 * 1024;
- case CACHE_SIZE_16_KB: return 16 * 1024;
+ case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_32_KB: return 32 * 1024;
case CACHE_SIZE_64_KB: return 64 * 1024;
case CACHE_SIZE_128_KB: return 128 * 1024;
default: return 0;
}
}
-
+
UINTN
EFIAPI
ArmDataCacheAssociativity (
@@ -88,7 +88,7 @@ ArmDataCacheAssociativity ( default: return 0;
}
}
-
+
UINTN
EFIAPI
ArmDataCacheLineLength (
@@ -101,7 +101,7 @@ ArmDataCacheLineLength ( default: return 0;
}
}
-
+
BOOLEAN
EFIAPI
ArmInstructionCachePresent (
@@ -115,7 +115,7 @@ ArmInstructionCachePresent ( default: return FALSE;
}
}
-
+
UINTN
EFIAPI
ArmInstructionCacheSize (
@@ -124,16 +124,16 @@ ArmInstructionCacheSize ( {
switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))
{
- case CACHE_SIZE_4_KB: return 4 * 1024;
+ case CACHE_SIZE_4_KB: return 4 * 1024;
case CACHE_SIZE_8_KB: return 8 * 1024;
- case CACHE_SIZE_16_KB: return 16 * 1024;
+ case CACHE_SIZE_16_KB: return 16 * 1024;
case CACHE_SIZE_32_KB: return 32 * 1024;
case CACHE_SIZE_64_KB: return 64 * 1024;
case CACHE_SIZE_128_KB: return 128 * 1024;
default: return 0;
}
}
-
+
UINTN
EFIAPI
ArmInstructionCacheAssociativity (
@@ -148,7 +148,7 @@ ArmInstructionCacheAssociativity ( default: return 0;
}
}
-
+
UINTN
EFIAPI
ArmInstructionCacheLineLength (
|