diff options
| author | Ronald Cron <ronald.cron@arm.com> | 2014-08-19 13:29:52 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-19 13:29:52 +0000 |
| commit | 3402aac7d985bf8a9f9d3c639f3fe93609380513 (patch) | |
| tree | 67b11334dc45181581aaaac236243fe72c7f614c /ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm | |
| parent | 62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 (diff) | |
| download | edk2-platforms-3402aac7d985bf8a9f9d3c639f3fe93609380513.tar.xz | |
ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm index fc87828e20..4aaa546ca0 100644 --- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm +++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
@@ -41,12 +41,12 @@ IC_ON EQU ( 0x1:SHL:12 ) ArmInvalidateDataCacheEntryByMVA
- MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
BX lr
ArmCleanDataCacheEntryByMVA
- MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
BX lr
@@ -60,7 +60,7 @@ ArmEnableInstructionCache ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
-
+
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -100,7 +100,7 @@ ArmEnableDataCache ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
-
+
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -121,7 +121,7 @@ ArmInvalidateDataCache MOV R0,#0
MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
-
+
ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
@@ -139,12 +139,12 @@ ASM_PFX(ArmDataMemoryBarrier): mov R0, #0
mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
bx LR
-
+
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
bx LR
-
+
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
|