diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-03-26 11:01:21 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-03-26 11:01:21 +0000 |
| commit | 18029bb9112f7af8c9aedcf0dacbdd5267eb258c (patch) | |
| tree | bde294a687b7f3e49738eddd01d2733373da40ab /ArmPkg/Library/ArmLib/ArmV7 | |
| parent | eac42a514b8bfd5d6273d673d8d24a424b579d1c (diff) | |
| download | edk2-platforms-18029bb9112f7af8c9aedcf0dacbdd5267eb258c.tar.xz | |
ArmLib/ArmV7: Add ISB to ArmEnableVFP
ArmEnableVFP could crash on an out-of-order CPU. Adding an instruction barrier after writing to CPACR cures the problem.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13134 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 1 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 3bb601541d..5ac3552403 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -347,6 +347,7 @@ ASM_PFX(ArmEnableVFP): orr r0, r0, #0x00f00000
# Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2
+ isb
# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000
mcr p10,#0x7,r0,c8,c0,#0
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 28a4564aca..8fedcdba97 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -341,6 +341,7 @@ ArmEnableVFP orr r0, r0, #0x00f00000
// Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2
+ isb
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000
mcr p10,#0x7,r0,c8,c0,#0
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