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| author | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-02-02 22:35:30 +0000 |
|---|---|---|
| committer | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-02-02 22:35:30 +0000 |
| commit | 1bfda055dfbc52678655ab2ded721f9f7c0cd496 (patch) | |
| tree | fbfa3654ec28d060955ff37e9e9365ad37179013 /ArmPkg/Library/ArmLib/Common | |
| parent | 7373d15a98fb571bf56688676c8ba950e6f62b8d (diff) | |
| download | edk2-platforms-1bfda055dfbc52678655ab2ded721f9f7c0cd496.tar.xz | |
Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib.h and fixed a lot of issues with Xcode building.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Common')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Common/ArmLibSupport.S | 51 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm | 18 |
2 files changed, 34 insertions, 35 deletions
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S index a432acbb80..9b144c82c5 100644 --- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S @@ -12,37 +12,24 @@ # #------------------------------------------------------------------------------ +#include <AsmMacroIoLib.h> + .text .align 2 -.globl ASM_PFX(Cp15IdCode) -INTERWORK_FUNC(Cp15IdCode) -.globl ASM_PFX(Cp15CacheInfo) -INTERWORK_FUNC(Cp15CacheInfo) -.globl ASM_PFX(ArmEnableInterrupts) -INTERWORK_FUNC(ArmEnableInterrupts) -.globl ASM_PFX(ArmDisableInterrupts) -INTERWORK_FUNC(ArmDisableInterrupts) -.globl ASM_PFX(ArmGetInterruptState) -INTERWORK_FUNC(ArmGetInterruptState) -.globl ASM_PFX(ArmEnableFiq) -INTERWORK_FUNC(ArmEnableFiq) -.globl ASM_PFX(ArmDisableFiq) -INTERWORK_FUNC(ArmDisableFiq) -.globl ASM_PFX(ArmGetFiqState) -INTERWORK_FUNC(ArmGetFiqState) -.globl ASM_PFX(ArmInvalidateTlb) -INTERWORK_FUNC(ArmInvalidateTlb) -.globl ASM_PFX(ArmSetTranslationTableBaseAddress) -INTERWORK_FUNC(ArmSetTranslationTableBaseAddress) -.globl ASM_PFX(ArmGetTranslationTableBaseAddress) -INTERWORK_FUNC(ArmGetTranslationTableBaseAddress) -.globl ASM_PFX(ArmSetDomainAccessControl) -INTERWORK_FUNC(ArmSetDomainAccessControl) -.globl ASM_PFX(CPSRMaskInsert) -INTERWORK_FUNC(CPSRMaskInsert) -.globl ASM_PFX(CPSRRead) -INTERWORK_FUNC(CPSRRead) - +GCC_ASM_EXPORT(Cp15IdCode) +GCC_ASM_EXPORT(Cp15CacheInfo) +GCC_ASM_EXPORT(ArmEnableInterrupts) +GCC_ASM_EXPORT(ArmDisableInterrupts) +GCC_ASM_EXPORT(ArmGetInterruptState) +GCC_ASM_EXPORT(ArmEnableFiq) +GCC_ASM_EXPORT(ArmDisableFiq) +GCC_ASM_EXPORT(ArmGetFiqState) +GCC_ASM_EXPORT(ArmInvalidateTlb) +GCC_ASM_EXPORT(ArmSetTTBR0) +GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) +GCC_ASM_EXPORT(ArmSetDomainAccessControl) +GCC_ASM_EXPORT(CPSRMaskInsert) +GCC_ASM_EXPORT(CPSRRead) #------------------------------------------------------------------------------ @@ -103,12 +90,14 @@ ASM_PFX(ArmInvalidateTlb): mcr p15,0,r0,c8,c7,0 bx lr -ASM_PFX(ArmSetTranslationTableBaseAddress): +ASM_PFX(ArmSetTTBR0): mcr p15,0,r0,c2,c0,0 bx lr -ASM_PFX(ArmGetTranslationTableBaseAddress): +ASM_PFX(ArmGetTTBR0BaseAddress): mrc p15,0,r0,c2,c0,0 + LoadConstantToReg(0xFFFFC000, r1) @ and r0, r0, #0xFFFFC000 + and r0, r0, r1 bx lr diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm index 459ebd44c8..cf7605f45a 100644 --- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm @@ -15,6 +15,7 @@ EXPORT Cp15IdCode EXPORT Cp15CacheInfo + EXPORT ArmIsMPCore EXPORT ArmEnableInterrupts EXPORT ArmDisableInterrupts EXPORT ArmGetInterruptState @@ -22,8 +23,8 @@ EXPORT ArmDisableFiq EXPORT ArmGetFiqState EXPORT ArmInvalidateTlb - EXPORT ArmSetTranslationTableBaseAddress - EXPORT ArmGetTranslationTableBaseAddress + EXPORT ArmSetTTBR0 + EXPORT ArmGetTTBR0BaseAddress EXPORT ArmSetDomainAccessControl EXPORT CPSRMaskInsert EXPORT CPSRRead @@ -38,6 +39,14 @@ Cp15CacheInfo mrc p15,0,R0,c0,c0,1 bx LR +ArmIsMPCore + mrc p15,0,R0,c0,c0,5 + # Get Multiprocessing extension (bit31) & U bit (bit30) + and R0, R0, #0xC0000000 + # if bit30 == 0 then the processor is part of a multiprocessor system) + and R0, R0, #0x80000000 + bx LR + ArmEnableInterrupts mrs R0,CPSR bic R0,R0,#0x80 ;Enable IRQ interrupts @@ -87,12 +96,13 @@ ArmInvalidateTlb mcr p15,0,r0,c8,c7,0 bx lr -ArmSetTranslationTableBaseAddress +ArmSetTTBR0 mcr p15,0,r0,c2,c0,0 bx lr -ArmGetTranslationTableBaseAddress +ArmGetTTBR0BaseAddress mrc p15,0,r0,c2,c0,0 + and r0, r0, #0xFFFFC000 bx lr ArmSetDomainAccessControl |