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| author | Olivier Martin <olivier.martin@arm.com> | 2014-03-24 15:26:22 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-03-24 15:26:22 +0000 |
| commit | 647517279d97297302780598122b80c8f4f855f1 (patch) | |
| tree | 0e1b2b5efd401a962c5875085d16d7635fc6543f /ArmPkg/Library/ArmLib/Common | |
| parent | d9bd3f11cb47f8026a44721670f4abdfb9728a2a (diff) | |
| download | edk2-platforms-647517279d97297302780598122b80c8f4f855f1.tar.xz | |
ArmPkg/ArmLib: Renamed Cp15CacheInfo into ArmCacheInfo
CTR (Cache Type Register) has the same format on ARMv7 and AArch64.
Renaming Cp15CacheInfo() into ArmCacheInfo() makes this function
architecture independent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15381 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Common')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S | 4 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S index a3de902cc6..f3b949565f 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S @@ -24,7 +24,7 @@ .text
.align 2
GCC_ASM_EXPORT(ArmReadMidr)
-GCC_ASM_EXPORT(Cp15CacheInfo)
+GCC_ASM_EXPORT(ArmCacheInfo)
GCC_ASM_EXPORT(ArmGetInterruptState)
GCC_ASM_EXPORT(ArmGetFiqState)
GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
@@ -54,7 +54,7 @@ ASM_PFX(ArmReadMidr): mrc p15,0,R0,c0,c0,0
bx LR
-ASM_PFX(Cp15CacheInfo):
+ASM_PFX(ArmCacheInfo):
mrc p15,0,R0,c0,c0,1
bx LR
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm index cb69f71bc7..2e26ff35cf 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm @@ -24,7 +24,7 @@ #endif
EXPORT ArmReadMidr
- EXPORT Cp15CacheInfo
+ EXPORT ArmCacheInfo
EXPORT ArmGetInterruptState
EXPORT ArmGetFiqState
EXPORT ArmGetTTBR0BaseAddress
@@ -54,7 +54,7 @@ ArmReadMidr mrc p15,0,R0,c0,c0,0
bx LR
-Cp15CacheInfo
+ArmCacheInfo
mrc p15,0,R0,c0,c0,1
bx LR
|