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authorandrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524>2011-02-02 23:19:30 +0000
committerandrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524>2011-02-02 23:19:30 +0000
commit2ac288f9199196dfc4ab05bee0a7815ca361174a (patch)
tree66ba7102ed0f7e8b6deab5416f868aa43c82ad50 /ArmPkg/Library/ArmLib
parent5d23922674950ec2d2654b4c606692696681b544 (diff)
downloadedk2-platforms-2ac288f9199196dfc4ab05bee0a7815ca361174a.tar.xz
Fix issue with fixing tabs.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11297 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib')
-rw-r--r--ArmPkg/Library/ArmLib/Arm9/Arm9Support.S12
-rw-r--r--ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm4
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm22
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S2
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm2
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S12
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm12
-rw-r--r--ArmPkg/Library/ArmLib/Common/ArmLibSupport.S52
-rw-r--r--ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm52
9 files changed, 85 insertions, 85 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
index badec4a72f..49e266dd38 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
@@ -58,18 +58,18 @@ ASM_PFX(ArmEnableInstructionCache):
orr r0,r0,r1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-\s\s
+
ASM_PFX(ArmDisableInstructionCache):
ldr r1,=IC_ON
mrc p15,0,r0,c1,c0,0 @Read control register configuration data
bic r0,r0,r1 @Clear I bit.
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-\s\s
+
ASM_PFX(ArmInvalidateInstructionCache):
mov r0,#0
mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
-\s\s @Also flushes the branch target cache.
+ @Also flushes the branch target cache.
mov r0,#0
mcr p15,0,r0,c7,c10,4 @Data write buffer
bx LR
@@ -99,7 +99,7 @@ ASM_PFX(ArmEnableDataCache):
orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-\s\s
+
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -111,7 +111,7 @@ ASM_PFX(ArmCleanDataCache):
mrc p15,0,r15,c7,c10,3
bne ASM_PFX(ArmCleanDataCache)
mov R0,#0
- mcr p15,0,R0,c7,c10,4\s\s@Drain write buffer
+ mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmInvalidateDataCache):
@@ -125,7 +125,7 @@ ASM_PFX(ArmCleanInvalidateDataCache):
mrc p15,0,r15,c7,c14,3
bne ASM_PFX(ArmCleanInvalidateDataCache)
mov R0,#0
- mcr p15,0,R0,c7,c10,4\s\s @Drain write buffer
+ mcr p15,0,R0,c7,c10,4 @Drain write buffer
bx LR
ASM_PFX(ArmEnableBranchPrediction):
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
index 2a147eff3a..dfee136b2b 100644
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
@@ -112,7 +112,7 @@ ArmCleanDataCache
MRC p15,0,r15,c7,c10,3
BNE ArmCleanDataCache
MOV R0,#0
- MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer
+ MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmInvalidateDataCache
@@ -126,7 +126,7 @@ ArmCleanInvalidateDataCache
MRC p15,0,r15,c7,c14,3
BNE ArmCleanInvalidateDataCache
MOV R0,#0
- MCR p15,0,R0,c7,c10,4\s\s ;Drain write buffer
+ MCR p15,0,R0,c7,c10,4 ;Drain write buffer
BX LR
ArmEnableBranchPrediction
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
index 831532f4d2..19f489f3c0 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm
@@ -70,17 +70,17 @@ ArmDisableAsynchronousAbort
ArmEnableIrq
cpsie i
isb
-\s\sbx LR
+ bx LR
ArmDisableIrq
cpsid i
isb
-\s\sbx LR
+ bx LR
ArmEnableFiq
cpsie f
isb
-\s\sbx LR
+ bx LR
ArmDisableFiq
cpsid f
@@ -99,17 +99,17 @@ ArmDisableInterrupts
ArmGetInterruptState
mrs R0,CPSR
- tst R0,#0x80\s\s ;Check if IRQ is enabled.
+ tst R0,#0x80 ;Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
-\s\sbx LR
+ bx LR
ArmGetFiqState
-\s\smrs R0,CPSR
-\s\stst R0,#0x40\s\s ;Check if FIQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
+ mrs R0,CPSR
+ tst R0,#0x40 ;Check if FIQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
ArmInvalidateTlb
mov r0,#0
@@ -126,7 +126,7 @@ ArmSetTTBR0
ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
- ldr\s\s r1, = 0xFFFFC000
+ ldr r1, = 0xFFFFC000
and r0, r0, r1
isb
bx lr
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
index 9d7b31efdc..da35a09b1d 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S
@@ -31,7 +31,7 @@ ASM_PFX(ArmGetScuBaseAddress):
# the Configuration BAR as a stack is not necessary setup. The SCU is at the
# offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
- bx\s\slr
+ bx lr
# IN None
# OUT r1 = SCU enabled (boolean)
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
index e87d231356..6cc17c4c6a 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm
@@ -31,7 +31,7 @@ ArmGetScuBaseAddress
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
- bx\s\slr
+ bx lr
// IN None
// OUT r1 = SCU enabled (boolean)
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 00704164f9..7dbbaf7d0f 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -80,21 +80,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\s\s\s\s
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
dsb
isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\s\s\s\s
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
dsb
isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line\s\s\s\s
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line
dsb
isb
bx lr
@@ -119,7 +119,7 @@ ASM_PFX(ArmDisableMmu):
bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 @Disable MMU
-\s\smcr \s\s\s\sp15,0,R0,c8,c7,0 @Invalidate TLB
+ mcr p15,0,R0,c8,c7,0 @Invalidate TLB
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
dsb
isb
@@ -309,7 +309,7 @@ ASM_PFX(ArmCallWFI):
//Note: Return 0 in Uniprocessor implementation
ASM_PFX(ArmReadCbar):
- mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
+ mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
@@ -318,7 +318,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb):
bx lr
ASM_PFX(ArmReadMpidr):
- mrc p15, 0, r0, c0, c0, 5\s\s @ read MPIDR
+ mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index 4cd78d8a23..4c78c54674 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -82,21 +82,21 @@ ArmCleanInvalidateDataCacheEntryByMVA
ArmInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\s\s\s\s
+ mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
dsb
isb
bx lr
ArmCleanInvalidateDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\s\s\s\s
+ mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
dsb
isb
bx lr
ArmCleanDataCacheEntryBySetWay
- mcr p15, 0, r0, c7, c10, 2 ; Clean this line\s\s\s\s
+ mcr p15, 0, r0, c7, c10, 2 ; Clean this line
dsb
isb
bx lr
@@ -125,7 +125,7 @@ ArmDisableMmu
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
- mcr \s\s p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
+ mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
dsb
isb
@@ -307,7 +307,7 @@ ArmCallWFI
//Note: Return 0 in Uniprocessor implementation
ArmReadCbar
- mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
+ mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr
ArmInvalidateInstructionAndDataTlb
@@ -316,7 +316,7 @@ ArmInvalidateInstructionAndDataTlb
bx lr
ArmReadMpidr
- mrc p15, 0, r0, c0, c0, 5\s\s\s\s; read MPIDR
+ mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
bx lr
END
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
index 94b11a5d77..29ccf6dceb 100644
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
@@ -42,48 +42,48 @@ ASM_PFX(Cp15CacheInfo):
bx LR
ASM_PFX(ArmEnableInterrupts):
-\s\smrs R0,CPSR
-\s\sbic R0,R0,#0x80\s\s\s\s@Enable IRQ interrupts
-\s\smsr CPSR_c,R0
-\s\sbx LR
+ mrs R0,CPSR
+ bic R0,R0,#0x80 @Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
ASM_PFX(ArmDisableInterrupts):
-\s\smrs R0,CPSR
-\s\sorr R1,R0,#0x80\s\s\s\s@Disable IRQ interrupts
-\s\smsr CPSR_c,R1
+ mrs R0,CPSR
+ orr R1,R0,#0x80 @Disable IRQ interrupts
+ msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
-\s\sbx LR
+ bx LR
ASM_PFX(ArmGetInterruptState):
-\s\smrs R0,CPSR
-\s\stst R0,#0x80\s\s @Check if IRQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
+ mrs R0,CPSR
+ tst R0,#0x80 @Check if IRQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
ASM_PFX(ArmEnableFiq):
-\s\smrs R0,CPSR
-\s\sbic R0,R0,#0x40\s\s\s\s@Enable FIQ interrupts
-\s\smsr CPSR_c,R0
-\s\sbx LR
+ mrs R0,CPSR
+ bic R0,R0,#0x40 @Enable FIQ interrupts
+ msr CPSR_c,R0
+ bx LR
ASM_PFX(ArmDisableFiq):
-\s\smrs R0,CPSR
-\s\sorr R1,R0,#0x40\s\s\s\s@Disable FIQ interrupts
-\s\smsr CPSR_c,R1
+ mrs R0,CPSR
+ orr R1,R0,#0x40 @Disable FIQ interrupts
+ msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
-\s\sbx LR
+ bx LR
ASM_PFX(ArmGetFiqState):
-\s\smrs R0,CPSR
-\s\stst R0,#0x80\s\s @Check if FIQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
+ mrs R0,CPSR
+ tst R0,#0x80 @Check if FIQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
ASM_PFX(ArmInvalidateTlb):
mov r0,#0
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
index 0b023fed42..4d6c253cd2 100644
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -48,48 +48,48 @@ ArmIsMPCore
bx LR
ArmEnableInterrupts
-\s\smrs R0,CPSR
-\s\sbic R0,R0,#0x80\s\s\s\s;Enable IRQ interrupts
-\s\smsr CPSR_c,R0
-\s\sbx LR
+ mrs R0,CPSR
+ bic R0,R0,#0x80 ;Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
ArmDisableInterrupts
-\s\smrs R0,CPSR
-\s\sorr R1,R0,#0x80\s\s\s\s;Disable IRQ interrupts
-\s\smsr CPSR_c,R1
+ mrs R0,CPSR
+ orr R1,R0,#0x80 ;Disable IRQ interrupts
+ msr CPSR_c,R1
tst R0,#0x80
moveq R0,#1
movne R0,#0
-\s\sbx LR
+ bx LR
ArmGetInterruptState
-\s\smrs R0,CPSR
-\s\stst R0,#0x80\s\s ;Check if IRQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
+ mrs R0,CPSR
+ tst R0,#0x80 ;Check if IRQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
ArmEnableFiq
-\s\smrs R0,CPSR
-\s\sbic R0,R0,#0x40\s\s\s\s;Enable IRQ interrupts
-\s\smsr CPSR_c,R0
-\s\sbx LR
+ mrs R0,CPSR
+ bic R0,R0,#0x40 ;Enable IRQ interrupts
+ msr CPSR_c,R0
+ bx LR
ArmDisableFiq
-\s\smrs R0,CPSR
-\s\sorr R1,R0,#0x40\s\s\s\s;Disable IRQ interrupts
-\s\smsr CPSR_c,R1
+ mrs R0,CPSR
+ orr R1,R0,#0x40 ;Disable IRQ interrupts
+ msr CPSR_c,R1
tst R0,#0x40
moveq R0,#1
movne R0,#0
-\s\sbx LR
+ bx LR
ArmGetFiqState
-\s\smrs R0,CPSR
-\s\stst R0,#0x40\s\s ;Check if IRQ is enabled.
-\s\smoveq R0,#1
-\s\smovne R0,#0
-\s\sbx LR
+ mrs R0,CPSR
+ tst R0,#0x40 ;Check if IRQ is enabled.
+ moveq R0,#1
+ movne R0,#0
+ bx LR
ArmInvalidateTlb
mov r0,#0