diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-06-03 09:18:48 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-06-03 09:18:48 +0000 |
| commit | 63adfb112944b5b46653711e7588c5c1163017a3 (patch) | |
| tree | c173455af381d8ef8036f88bd4e439d91ac42346 /ArmPkg/Library/ArmLib | |
| parent | eeec69c5dc62460d2b256f3dee8097fb7afb34d5 (diff) | |
| download | edk2-platforms-63adfb112944b5b46653711e7588c5c1163017a3.tar.xz | |
Armkg: Fix EDK2 coding style
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11734 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c | 4 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c index 65c09a1a35..929140774c 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c @@ -50,8 +50,8 @@ ArmInvalidScu ( scu_base = ArmGetScuBaseAddress(); - /* Invalidate all: write -1 to SCU Invalidate All register */ + // Invalidate all: write -1 to SCU Invalidate All register MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff); - /* Enable SCU */ + // Enable SCU MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1); } diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 7dbbaf7d0f..5b12d1dee2 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -295,21 +295,21 @@ ASM_PFX(ArmWriteCPACR): bx lr ASM_PFX(ArmEnableVFP): - // Enable VFP registers + # Enable VFP registers mrc p15, 0, r0, c1, c0, 2 - orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + orr r0, r0, #0x00f00000 @ Enable VPF access (V* instructions) mcr p15, 0, r0, c1, c0, 2 - mov r0, #0x40000000 // Set EN bit in FPEXC - mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly + mov r0, #0x40000000 @ Set EN bit in FPEXC + mcr p10,#0x7,r0,c8,c0,#0 @ msr FPEXC,r0 in ARM assembly bx lr ASM_PFX(ArmCallWFI): wfi bx lr -//Note: Return 0 in Uniprocessor implementation +#Note: Return 0 in Uniprocessor implementation ASM_PFX(ArmReadCbar): - mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register + mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register bx lr ASM_PFX(ArmInvalidateInstructionAndDataTlb): |