diff options
| author | Olivier Martin <olivier.martin@arm.com> | 2014-06-03 16:37:29 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-06-03 16:37:29 +0000 |
| commit | 01674afdad3460f1c1f5f7a941c4c5895c8c3f86 (patch) | |
| tree | f0a06e07830cb71b1052fd2976da5420b1966106 /ArmPkg/Library | |
| parent | 8b7f930a14d1d5480b707b60323e95450e7361c1 (diff) | |
| download | edk2-platforms-01674afdad3460f1c1f5f7a941c4c5895c8c3f86.tar.xz | |
ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations.
Cache maintenance operations by Set/Way require that the Write Buffer
be drained before the cache is flushed. Without that, the flush can
miss the most recent values written as they are still "pipelined".
That has unfortunate consequences, especially where code is being
copied to RAM.
The fix is to add DSB instructions before the affected operations.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library')
| -rw-r--r-- | ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c | 2 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 6 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c | 5 |
3 files changed, 12 insertions, 1 deletions
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index 2557a2cf09..f4c12e7173 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -1,6 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -28,6 +29,7 @@ CacheRangeOperation ( UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
+ ArmDrainWriteBuffer ();
CacheOperation ();
} else {
// Align address (rounding down)
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c index fd7f14f9cf..a4e1f20ad9 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -1,7 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+ Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -232,6 +232,7 @@ ArmInvalidateDataCache ( VOID
)
{
+ ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
}
@@ -241,6 +242,7 @@ ArmCleanInvalidateDataCache ( VOID
)
{
+ ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
}
@@ -250,6 +252,7 @@ ArmCleanDataCache ( VOID
)
{
+ ArmDrainWriteBuffer ();
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
@@ -259,5 +262,6 @@ ArmCleanDataCacheToPoU ( VOID
)
{
+ ArmDrainWriteBuffer ();
AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c index cc5074bfc2..65709780ed 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c @@ -1,6 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -233,6 +234,7 @@ ArmInvalidateDataCache ( VOID
)
{
+ ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
}
@@ -242,6 +244,7 @@ ArmCleanInvalidateDataCache ( VOID
)
{
+ ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
}
@@ -251,6 +254,7 @@ ArmCleanDataCache ( VOID
)
{
+ ArmDrainWriteBuffer ();
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
@@ -260,5 +264,6 @@ ArmCleanDataCacheToPoU ( VOID
)
{
+ ArmDrainWriteBuffer ();
ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}
|