diff options
| author | Roy Franz <roy.franz@linaro.org> | 2013-09-02 09:10:17 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-09-02 09:10:17 +0000 |
| commit | c6ba1c12851d4e628410094684a697006a465628 (patch) | |
| tree | 6def2a4d1960a962e03cd0305f858a35fdfcf243 /ArmPkg/Library | |
| parent | 8c1e795168bf0b63252e7ad293324fe5e2c5abe3 (diff) | |
| download | edk2-platforms-c6ba1c12851d4e628410094684a697006a465628.tar.xz | |
ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 2 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 910e50e401..ee6eb41709 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -211,7 +211,7 @@ ASM_PFX(ArmSetLowVectors): ASM_PFX(ArmSetHighVectors):
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00002000 @ clear V bit
+ orr r0, r0, #0x00002000 @ Set V bit
mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 8035400599..e75438844d 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -209,7 +209,7 @@ ArmSetLowVectors ArmSetHighVectors
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
- orr r0, r0, #0x00002000 ; clear V bit
+ orr r0, r0, #0x00002000 ; Set V bit
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
|