Added support for L2 (4K) page tables and made the CPU driver change cachability attributes on request. Also got the DebugUncache infrastructure working for the first time. Looks like it works for the simple case. Checking in so we can get more eyes looking at the code.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9734 6f19259b-4bc3-4df7-8a09-765794883524

4 files changed, 12 insertions, 16 deletions

diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index 7da6b42a92..b5754e6dca 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -27,19 +27,15 @@ CacheRangeOperation (
   UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
   UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
   
-  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
-  {
-    CacheOperation();
-  }
-  else
-  {
+  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
+    CacheOperation ();
+  } else {
     // Align address (rounding down)
     UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
     UINTN EndAddress     = (UINTN)Start + Length;
 
     // Perform the line operation on an address in each cache line
-    while (AlignedAddress < EndAddress)
-    {
+    while (AlignedAddress < EndAddress) {
       LineOperation(AlignedAddress);
       AlignedAddress += ArmCacheLineLength;
     }
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
index ecae8a31a2..630c72fdee 100644
--- a/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
@@ -66,7 +66,7 @@ ArmSetTranslationTableBaseAddress
   mcr     p15,0,r0,c2,c0,0
   bx      lr
 
-ArmSetTranslationTableBaseAddress
+ArmGetTranslationTableBaseAddress
   mrc     p15,0,r0,c2,c0,0
   bx      lr
 
diff --git a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
index b4c1c5f2e5..80e7c8c472 100644
--- a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
+++ b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.c
@@ -49,7 +49,7 @@ UncachedInternalAllocateAlignedPages (
   

   

 

-EFI_CPU_ARCH_PROTOCOL           *gCpu;

+EFI_CPU_ARCH_PROTOCOL           *gDebugUncachedCpu;

 VIRTUAL_UNCACHED_PAGES_PROTOCOL *gVirtualUncachedPages;

 

 //

@@ -641,7 +641,7 @@ DebugUncachedMemoryAllocationLibConstructor (
 {

   EFI_STATUS    Status;

   

-  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);

+  Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gDebugUncachedCpu);

   ASSERT_EFI_ERROR(Status);

 

   Status = gBS->LocateProtocol (&gVirtualUncachedPagesProtocolGuid, NULL, (VOID **)&gVirtualUncachedPages);

diff --git a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
index 102ef78010..9cf29015d5 100644
--- a/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
+++ b/ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf
@@ -29,19 +29,19 @@
   MdePkg/MdePkg.dec

   ArmPkg/ArmPkg.dec

 

-[Protocols]

-  gEfiCpuArchProtocolGuid

 

 [LibraryClasses]

   BaseLib

-  UefiMemoryAllocationLib

+  MemoryAllocationLib

   ArmLib

 

+[Protocols]

+  gEfiCpuArchProtocolGuid

+  gVirtualUncachedPagesProtocolGuid

 

 [FixedPcd]

   gArmTokenSpaceGuid.PcdArmUncachedMemoryMask

   

   

 [Depex]

-  gEfiCpuArchProtocolGuid

-  gVirtualUncachedPagesProtocolGuid
\ No newline at end of file
+  gEfiCpuArchProtocolGuid AND gVirtualUncachedPagesProtocolGuid
\ No newline at end of file