ArmPkg: Add ARM Architectural Timer support

ARM Architectural Timer support is defined by the ARM Generic Timer Specification.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12455 6f19259b-4bc3-4df7-8a09-765794883524

8 files changed, 762 insertions, 0 deletions

diff --git a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
new file mode 100644
index 0000000000..d6f3f1b709
--- /dev/null
+++ b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
@@ -0,0 +1,191 @@
+/** @file

+  Generic ARM implementation of TimerLib.h

+

+  Copyright (c) 2011, ARM Limited. All rights reserved.

+  

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+

+

+#include <Base.h>

+#include <Library/BaseLib.h>

+#include <Library/TimerLib.h>

+#include <Library/DebugLib.h>

+#include <Library/PcdLib.h>

+#include <Library/ArmV7ArchTimerLib.h>

+#include <Chipset/ArmV7.h>

+

+#define TICKS_PER_MICRO_SEC     (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)

+

+RETURN_STATUS

+EFIAPI

+ArmArchTimerLibConstructor (

+  VOID

+  )

+{

+  // Check if the ARM Generic Timer Extension is implemented

+  if (ArmIsArchTimerImplemented ()) {

+

+    UINTN TimerFreq;

+

+    // Check if Architectural Timer frequency is valid number (should not be 0)

+    ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));

+

+    // Check if ticks/uS is not 0. The Architectural timer runs at constant

+    // frequency irrespective of CPU frequency. According to General Timer Ref

+    // manual lower bound of the frequency is in the range of 1-10MHz

+    ASSERT (TICKS_PER_MICRO_SEC);

+

+    // If the security extensions are not implemented set Timer Frequency

+    if ((ArmReadIdPfr1 () & 0xF0)) {

+      ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));

+    }

+

+    // Architectural Timer Frequency must be set in the Secure privileged(if secure extensions are supported) mode.

+    // If the reset value (0) is returned just ASSERT.

+    TimerFreq = ArmArchTimerGetTimerFreq ();

+    ASSERT (TimerFreq);

+

+  } else {

+    DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, Hence cann't use this library \n"));

+    ASSERT (0);

+  }

+

+  return RETURN_SUCCESS;

+}

+

+

+/**

+  Stalls the CPU for the number of microseconds specified by MicroSeconds.

+

+  @param  MicroSeconds  The minimum number of microseconds to delay.

+

+  @return The value of MicroSeconds inputted.

+

+**/

+UINTN

+EFIAPI

+MicroSecondDelay (

+  IN      UINTN                     MicroSeconds

+  )

+{

+  UINT64 TimerTicks64;

+  UINT64 SystemCounterVal;

+

+  // Calculate counter ticks that can represent requsted delay

+  TimerTicks64 = MultU64x32 (MicroSeconds, TICKS_PER_MICRO_SEC);

+

+  // Read System Counter value

+  SystemCounterVal = ArmArchTimerGetSystemCount ();

+

+  TimerTicks64 += SystemCounterVal;

+

+  // Wait until delay count is expired.

+  while (SystemCounterVal < TimerTicks64) {

+    SystemCounterVal = ArmArchTimerGetSystemCount ();

+  }

+

+  return MicroSeconds;

+}

+

+

+/**

+  Stalls the CPU for at least the given number of nanoseconds.

+

+  Stalls the CPU for the number of nanoseconds specified by NanoSeconds.

+

+  When the timer frequency is 1MHz, each tick corresponds to 1 microsecond.

+  Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond.

+

+  @param  NanoSeconds The minimum number of nanoseconds to delay.

+

+  @return The value of NanoSeconds inputted.

+

+**/

+UINTN

+EFIAPI

+NanoSecondDelay (

+  IN  UINTN NanoSeconds

+  )

+{

+  UINTN  MicroSeconds;

+

+  // Round up to 1us Tick Number

+  MicroSeconds = NanoSeconds / 1000;

+  MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;

+

+  MicroSecondDelay (MicroSeconds);

+

+  return NanoSeconds;

+}

+

+/**

+  Retrieves the current value of a 64-bit free running performance counter.

+

+  The counter can either count up by 1 or count down by 1. If the physical

+  performance counter counts by a larger increment, then the counter values

+  must be translated. The properties of the counter can be retrieved from

+  GetPerformanceCounterProperties().

+

+  @return The current value of the free running performance counter.

+

+**/

+UINT64

+EFIAPI

+GetPerformanceCounter (

+  VOID

+  )

+{

+  // Just return the value of system count

+  return ArmArchTimerGetSystemCount ();

+}

+

+/**

+  Retrieves the 64-bit frequency in Hz and the range of performance counter

+  values.

+

+  If StartValue is not NULL, then the value that the performance counter starts

+  with immediately after is it rolls over is returned in StartValue. If

+  EndValue is not NULL, then the value that the performance counter end with

+  immediately before it rolls over is returned in EndValue. The 64-bit

+  frequency of the performance counter in Hz is always returned. If StartValue

+  is less than EndValue, then the performance counter counts up. If StartValue

+  is greater than EndValue, then the performance counter counts down. For

+  example, a 64-bit free running counter that counts up would have a StartValue

+  of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter

+  that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.

+

+  @param  StartValue  The value the performance counter starts with when it

+                      rolls over.

+  @param  EndValue    The value that the performance counter ends with before

+                      it rolls over.

+

+  @return The frequency in Hz.

+

+**/

+UINT64

+EFIAPI

+GetPerformanceCounterProperties (

+  OUT      UINT64                    *StartValue,  OPTIONAL

+  OUT      UINT64                    *EndValue     OPTIONAL

+  )

+{

+  if (StartValue != NULL) {

+    // Timer starts with the reload value

+    *StartValue = (UINT64)0ULL ;

+  }

+

+  if (EndValue != NULL) {

+    // Timer counts down to 0x0

+    *EndValue = 0xFFFFFFFFFFFFFFFF;;

+  }

+

+  return (UINT64)ArmArchTimerGetTimerFreq ();

+}

diff --git a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
new file mode 100644
index 0000000000..87548b4851
--- /dev/null
+++ b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
@@ -0,0 +1,46 @@
+#/** @file

+#  

+#  Copyright (c) 2011, ARM Limited. All rights reserved.<BR>

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution.  The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php

+#  

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#  

+#**/

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = ArmArchTimerLib

+  FILE_GUID                      = 82da1b44-d2d6-4a7d-bbf0-a0cb67964034

+  MODULE_TYPE                    = BASE

+  VERSION_STRING                 = 1.0

+  LIBRARY_CLASS                  = TimerLib 

+  CONSTRUCTOR                    = ArmArchTimerLibConstructor

+

+[Sources.common]

+  ArmArchTimerLib.c

+

+[Packages]

+  MdePkg/MdePkg.dec

+  EmbeddedPkg/EmbeddedPkg.dec

+  ArmPkg/ArmPkg.dec

+  

+

+[LibraryClasses]

+  DebugLib

+  IoLib

+  ArmLib

+  BaseLib    

+  

+[Protocols]

+  

+[Guids]

+ 

+[Pcd]

+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz

+

+[Depex]

+  gEfiCpuArchProtocolGuid

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
new file mode 100644
index 0000000000..1cba12d300
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
@@ -0,0 +1,275 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#include <Uefi.h> 
+#include <Chipset/ArmV7.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include "ArmV7Lib.h"
+#include "ArmLibPrivate.h"
+#include <Library/ArmV7ArchTimerLib.h>
+
+VOID
+EFIAPI
+ArmArchTimerReadReg (
+    IN   ARM_ARCH_TIMER_REGS   Reg,
+    OUT  VOID                  *DstBuf
+    )
+{
+  // Check if the Generic/Architecture timer is implemented
+  if (ArmIsArchTimerImplemented ()) {
+
+    switch (Reg) {
+
+    case CntFrq:
+      *((UINTN *)DstBuf) = ArmReadCntFrq ();
+      break;
+
+    case CntPct:
+      *((UINT64 *)DstBuf) = ArmReadCntPct ();
+      break;
+
+    case CntkCtl:
+      *((UINTN *)DstBuf) = ArmReadCntkCtl();
+      break;
+
+    case CntpTval:
+      *((UINTN *)DstBuf) = ArmReadCntpTval ();
+      break;
+
+    case CntpCtl:
+      *((UINTN *)DstBuf) = ArmReadCntpCtl ();
+      break;
+
+    case CntvTval:
+      *((UINTN *)DstBuf) = ArmReadCntvTval ();
+      break;
+
+    case CntvCtl:
+      *((UINTN *)DstBuf) = ArmReadCntvCtl ();
+      break;
+
+    case CntvCt:
+      *((UINT64 *)DstBuf) = ArmReadCntvCt ();
+      break;
+
+    case CntpCval:
+      *((UINT64 *)DstBuf) = ArmReadCntpCval ();
+      break;
+
+    case CntvCval:
+      *((UINT64 *)DstBuf) = ArmReadCntvCval ();
+      break;
+
+    case CntvOff:
+      *((UINT64 *)DstBuf) = ArmReadCntvOff ();
+      break;
+
+    case CnthCtl:
+    case CnthpTval:
+    case CnthpCtl:
+    case CnthpCval:
+    DEBUG ((EFI_D_ERROR, "The register is related to Hyperviser Mode. Can't perform requested operation\n "));
+      break;
+
+    default:
+      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
+    }
+  } else {
+    DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
+    ASSERT (0);
+  }
+}
+
+VOID
+EFIAPI
+ArmArchTimerWriteReg (
+    IN   ARM_ARCH_TIMER_REGS   Reg,
+    IN   VOID                  *SrcBuf
+    )
+{
+  // Check if the Generic/Architecture timer is implemented
+  if (ArmIsArchTimerImplemented ()) {
+
+    switch (Reg) {
+
+    case CntFrq:
+      ArmWriteCntFrq (*((UINTN *)SrcBuf));
+      break;
+
+    case CntPct:
+      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
+      break;
+
+    case CntkCtl:
+      ArmWriteCntkCtl (*((UINTN *)SrcBuf));
+      break;
+
+    case CntpTval:
+      ArmWriteCntpTval (*((UINTN *)SrcBuf));
+      break;
+
+    case CntpCtl:
+      ArmWriteCntpCtl (*((UINTN *)SrcBuf));
+      break;
+
+    case CntvTval:
+      ArmWriteCntvTval (*((UINTN *)SrcBuf));
+      break;
+
+    case CntvCtl:
+      ArmWriteCntvCtl (*((UINTN *)SrcBuf));
+      break;
+
+    case CntvCt:
+      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
+      break;
+
+    case CntpCval:
+      ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
+      break;
+
+    case CntvCval:
+      ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
+      break;
+
+    case CntvOff:
+      ArmWriteCntvOff (*((UINT64 *)SrcBuf));
+      break;
+
+    case CnthCtl:
+    case CnthpTval:
+    case CnthpCtl:
+    case CnthpCval:
+      DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
+      break;
+
+    default:
+      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
+    }
+  } else {
+    DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
+    ASSERT (0);
+  }
+}
+
+VOID
+EFIAPI
+ArmArchTimerEnableTimer (
+    VOID
+    )
+{
+  UINTN TimerCtrlReg;
+
+  ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
+  TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
+  ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
+}
+
+VOID
+EFIAPI
+ArmArchTimerDisableTimer (
+    VOID
+    )
+{
+  UINTN TimerCtrlReg;
+
+  ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
+  TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
+  ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
+}
+
+VOID
+EFIAPI
+ArmArchTimerSetTimerFreq (
+    IN   UINTN  FreqInHz
+    )
+{
+  ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
+}
+
+UINTN
+EFIAPI
+ArmArchTimerGetTimerFreq (
+    VOID
+    )
+{
+  UINTN ArchTimerFreq = 0;
+  ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
+  return ArchTimerFreq;
+}
+
+UINTN
+EFIAPI
+ArmArchTimerGetTimerVal (
+    VOID
+    )
+{
+  UINTN ArchTimerVal;
+  ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
+  return ArchTimerVal;
+}
+
+
+VOID
+EFIAPI
+ArmArchTimerSetTimerVal (
+    IN   UINTN   Val
+    )
+{
+  ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
+}
+
+UINT64
+EFIAPI
+ArmArchTimerGetSystemCount (
+    VOID
+    )
+{
+  UINT64 SystemCount;
+  ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
+  return SystemCount;
+}
+
+UINTN
+EFIAPI
+ArmArchTimerGetTimerCtrlReg (
+    VOID
+    )
+{
+  UINTN  Val;
+  ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
+  return Val;
+}
+
+VOID
+EFIAPI
+ArmArchTimerSetTimerCtrlReg (
+    UINTN Val
+    )
+{
+  ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
+}
+
+VOID
+EFIAPI
+ArmArchTimerSetCompareVal (
+    IN   UINT64   Val
+    )
+{
+  ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
+}
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
new file mode 100644
index 0000000000..531d8fd1e0
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
@@ -0,0 +1,119 @@
+#------------------------------------------------------------------------------ 

+#

+# Copyright (c) 2011, ARM Limited. All rights reserved.

+#

+# This program and the accompanying materials

+# are licensed and made available under the terms and conditions of the BSD License

+# which accompanies this distribution.  The full text of the license may be found at

+# http://opensource.org/licenses/bsd-license.php

+#

+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+#------------------------------------------------------------------------------

+

+.text

+.align 2

+

+GCC_ASM_EXPORT (ArmReadCntFrq)

+GCC_ASM_EXPORT (ArmWriteCntFrq)

+GCC_ASM_EXPORT (ArmReadCntPct)

+GCC_ASM_EXPORT (ArmReadCntkCtl)

+GCC_ASM_EXPORT (ArmWriteCntkCtl)

+GCC_ASM_EXPORT (ArmReadCntpTval)

+GCC_ASM_EXPORT (ArmWriteCntpTval)

+GCC_ASM_EXPORT (ArmReadCntpCtl)

+GCC_ASM_EXPORT (ArmWriteCntpCtl)

+GCC_ASM_EXPORT (ArmReadCntvTval)

+GCC_ASM_EXPORT (ArmWriteCntvTval)

+GCC_ASM_EXPORT (ArmReadCntvCtl)

+GCC_ASM_EXPORT (ArmWriteCntvCtl)

+GCC_ASM_EXPORT (ArmReadCntvCt)

+GCC_ASM_EXPORT (ArmReadCntpCval)

+GCC_ASM_EXPORT (ArmWriteCntpCval)

+GCC_ASM_EXPORT (ArmReadCntvCval)

+GCC_ASM_EXPORT (ArmWriteCntvCval)

+GCC_ASM_EXPORT (ArmReadCntvOff)

+GCC_ASM_EXPORT (ArmWriteCntvOff)

+

+ASM_PFX(ArmReadCntFrq):

+  mrc    p15, 0, r0, c14, c0, 0    @ Read CNTFRQ

+  bx     lr

+

+ASM_PFX(ArmWriteCntFrq):

+  mcr    p15, 0, r0, c14, c0, 0    @ Write to CNTFRQ

+  bx     lr

+

+ASM_PFX(ArmReadCntPct):

+  mrrc   p15, 0, r0, r1, c14       @ Read CNTPT (Physical counter register)

+  bx     lr

+

+ASM_PFX(ArmReadCntkCtl):

+  mrc    p15, 0, r0, c14, c1, 0    @ Read CNTK_CTL (Timer PL1 Control Register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntkCtl):

+  mcr    p15, 0, r0, c14, c1, 0    @ Write to CNTK_CTL (Timer PL1 Control Register)

+  bx     lr

+

+ASM_PFX(ArmReadCntpTval):

+  mrc    p15, 0, r0, c14, c2, 0    @ Read CNTP_TVAL (PL1 physical timer value register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntpTval):

+  mcr    p15, 0, r0, c14, c2, 0    @ Write to CNTP_TVAL (PL1 physical timer value register)

+  bx     lr

+

+ASM_PFX(ArmReadCntpCtl):

+  mrc    p15, 0, r0, c14, c2, 1    @ Read CNTP_CTL (PL1 Physical Timer Control Register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntpCtl):

+  mcr    p15, 0, r0, c14, c2, 1    @ Write to  CNTP_CTL (PL1 Physical Timer Control Register)

+  bx     lr

+

+ASM_PFX(ArmReadCntvTval):

+  mrc    p15, 0, r0, c14, c3, 0    @ Read CNTV_TVAL (Virtual Timer Value register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntvTval):

+  mcr    p15, 0, r0, c14, c3, 0    @ Write to CNTV_TVAL (Virtual Timer Value register)

+  bx     lr

+

+ASM_PFX(ArmReadCntvCtl):

+  mrc    p15, 0, r0, c14, c3, 1    @ Read CNTV_CTL (Virtual Timer Control Register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntvCtl):

+  mcr    p15, 0, r0, c14, c3, 1    @ Write to CNTV_CTL (Virtual Timer Control Register)

+  bx     lr

+

+ASM_PFX(ArmReadCntvCt):

+  mrrc   p15, 1, r0, r1, c14       @ Read CNTVCT  (Virtual Count Register)

+  bx     lr

+

+ASM_PFX(ArmReadCntpCval):

+  mrrc   p15, 2, r0, r1, c14       @ Read CNTP_CTVAL (Physical Timer Compare Value Register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntpCval):

+  mcrr   p15, 2, r0, r1, c14       @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)

+  bx     lr

+

+ASM_PFX(ArmReadCntvCval):

+  mrrc   p15, 3, r0, r1, c14       @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntvCval):

+  mcrr   p15, 3, r0, r1, c14       @ write to  CNTV_CTVAL (Virtual Timer Compare Value Register)

+  bx     lr

+

+ASM_PFX(ArmReadCntvOff):

+  mrrc   p15, 4, r0, r1, c14       @ Read CNTVOFF (virtual Offset register)

+  bx     lr

+

+ASM_PFX(ArmWriteCntvOff):

+  mcrr   p15, 4, r0, r1, c14       @ Write to CNTVOFF (Virtual Offset register)

+  bx     lr

+

+ASM_FUNCTION_REMOVE_IF_UNREFERENCED

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
new file mode 100644
index 0000000000..fc0be1966b
--- /dev/null
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
@@ -0,0 +1,119 @@
+//------------------------------------------------------------------------------ 

+//

+// Copyright (c) 2011, ARM Limited. All rights reserved.

+//

+// This program and the accompanying materials

+// are licensed and made available under the terms and conditions of the BSD License

+// which accompanies this distribution.  The full text of the license may be found at

+// http://opensource.org/licenses/bsd-license.php

+//

+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+//

+//------------------------------------------------------------------------------

+

+    EXPORT  ArmReadCntFrq

+    EXPORT  ArmWriteCntFrq

+    EXPORT  ArmReadCntPct

+    EXPORT  ArmReadCntkCtl

+    EXPORT  ArmWriteCntkCtl

+    EXPORT  ArmReadCntpTval

+    EXPORT  ArmWriteCntpTval

+    EXPORT  ArmReadCntpCtl

+    EXPORT  ArmWriteCntpCtl

+    EXPORT  ArmReadCntvTval

+    EXPORT  ArmWriteCntvTval

+    EXPORT  ArmReadCntvCtl

+    EXPORT  ArmWriteCntvCtl

+    EXPORT  ArmReadCntvCt

+    EXPORT  ArmReadCntpCval

+    EXPORT  ArmWriteCntpCval

+    EXPORT  ArmReadCntvCval

+    EXPORT  ArmWriteCntvCval

+    EXPORT  ArmReadCntvOff

+    EXPORT  ArmWriteCntvOff

+

+    AREA    ArmV7ArchTimerSupport, CODE, READONLY

+    PRESERVE8

+

+ArmReadCntFrq

+  mrc    p15, 0, r0, c14, c0, 0    ; Read CNTFRQ

+  bx     lr

+

+ArmWriteCntFrq

+  mcr    p15, 0, r0, c14, c0, 0    ; Write to CNTFRQ

+  bx     lr

+

+ArmReadCntPct

+  mrrc   p15, 0, r0, r1, c14       ; Read CNTPT (Physical counter register)

+  bx     lr

+

+ArmReadCntkCtl

+  mrc    p15, 0, r0, c14, c1, 0    ; Read CNTK_CTL (Timer PL1 Control Register)

+  bx     lr

+

+ArmWriteCntkCtl

+  mcr    p15, 0, r0, c14, c1, 0    ; Write to CNTK_CTL (Timer PL1 Control Register)

+  bx     lr

+

+ArmReadCntpTval

+  mrc    p15, 0, r0, c14, c2, 0    ; Read CNTP_TVAL (PL1 physical timer value register)

+  bx     lr

+

+ArmWriteCntpTval

+  mcr    p15, 0, r0, c14, c2, 0    ; Write to CNTP_TVAL (PL1 physical timer value register)

+  bx     lr

+

+ArmReadCntpCtl

+  mrc    p15, 0, r0, c14, c2, 1    ; Read CNTP_CTL (PL1 Physical Timer Control Register)

+  bx     lr

+

+ArmWriteCntpCtl

+  mcr    p15, 0, r0, c14, c2, 1    ; Write to  CNTP_CTL (PL1 Physical Timer Control Register)

+  bx     lr

+

+ArmReadCntvTval

+  mrc    p15, 0, r0, c14, c3, 0    ; Read CNTV_TVAL (Virtual Timer Value register)

+  bx     lr

+

+ArmWriteCntvTval

+  mcr    p15, 0, r0, c14, c3, 0    ; Write to CNTV_TVAL (Virtual Timer Value register)

+  bx     lr

+

+ArmReadCntvCtl

+  mrc    p15, 0, r0, c14, c3, 1    ; Read CNTV_CTL (Virtual Timer Control Register)

+  bx     lr

+

+ArmWriteCntvCtl

+  mcr    p15, 0, r0, c14, c3, 1    ; Write to CNTV_CTL (Virtual Timer Control Register)

+  bx     lr

+

+ArmReadCntvCt

+  mrrc   p15, 1, r0, r1, c14       ; Read CNTVCT  (Virtual Count Register)

+  bx     lr

+

+ArmReadCntpCval

+  mrrc   p15, 2, r0, r1, c14       ; Read CNTP_CTVAL (Physical Timer Compare Value Register)

+  bx     lr

+

+ArmWriteCntpCval

+  mcrr   p15, 2, r0, r1, c14       ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)

+  bx     lr

+

+ArmReadCntvCval

+  mrrc   p15, 3, r0, r1, c14       ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)

+  bx     lr

+

+ArmWriteCntvCval

+  mcrr   p15, 3, r0, r1, c14       ; write to  CNTV_CTVAL (Virtual Timer Compare Value Register)

+  bx     lr

+

+ArmReadCntvOff

+  mrrc   p15, 4, r0, r1, c14       ; Read CNTVOFF (virtual Offset register)

+  bx     lr

+

+ArmWriteCntvOff

+  mcrr   p15, 4, r0, r1, c14       ; Write to CNTVOFF (Virtual Offset register)

+  bx     lr

+

+ END

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
index 2f0ade9b8e..2bc01a9949 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
@@ -35,6 +35,10 @@
   ArmV7Lib.c

   ArmV7Mmu.c

 

+  ArmV7ArchTimer.c

+  ArmV7ArchTimerSupport.S    | GCC

+  ArmV7ArchTimerSupport.asm    | RVCT

+

 [Packages]

   ArmPkg/ArmPkg.dec

   MdePkg/MdePkg.dec

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
index 6211549742..5fdb044974 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
@@ -34,6 +34,10 @@
   

   ArmV7Lib.c

   ArmV7Mmu.c

+  

+  ArmV7ArchTimer.c

+  ArmV7ArchTimerSupport.S    | GCC

+  ArmV7ArchTimerSupport.asm  | RVCT

 

 [Packages]

   ArmPkg/ArmPkg.dec

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
index b7cb450462..9e6f17ec3e 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
@@ -31,6 +31,10 @@
   ArmV7Support.asm  | RVCT

 

   ArmV7Lib.c

+  

+  ArmV7ArchTimer.c

+  ArmV7ArchTimerSupport.S    | GCC

+  ArmV7ArchTimerSupport.asm    | RVCT

 

 [Packages]

   ArmPkg/ArmPkg.dec