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author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-03-17 08:54:11 +0100 |
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committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-03-22 14:39:02 +0100 |
commit | 02e261c3f8b8aca1221f53e3845275a8a2a82dc8 (patch) | |
tree | 6c8d4a1721f377c75568640bb749c806d5934264 /ArmPkg | |
parent | 0dbbaa557331fe2ba26c3e2d66be5d21d1f5f7bb (diff) | |
download | edk2-platforms-02e261c3f8b8aca1221f53e3845275a8a2a82dc8.tar.xz |
ArmPkg/ArmExceptionLib: stack FPSR on common path
We have three code paths to stack/unstack the exception context, one for
each of EL3, EL2 and EL1. However, they all access the same copy of FPSR
so move that access to the common path.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Diffstat (limited to 'ArmPkg')
-rw-r--r-- | ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S index c47974b81e..3117e710fa 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S @@ -286,26 +286,25 @@ ASM_PFX(CommonExceptionEntry): EL1_OR_EL2_OR_EL3(x1)
1:mrs x1, elr_el1 // Exception Link Register
mrs x2, spsr_el1 // Saved Processor Status Register 32bit
- mrs x3, fpsr // Floating point Status Register 32bit
mrs x4, esr_el1 // EL1 Exception syndrome register 32bit
mrs x5, far_el1 // EL1 Fault Address Register
b 4f
2:mrs x1, elr_el2 // Exception Link Register
mrs x2, spsr_el2 // Saved Processor Status Register 32bit
- mrs x3, fpsr // Floating point Status Register 32bit
mrs x4, esr_el2 // EL2 Exception syndrome register 32bit
mrs x5, far_el2 // EL2 Fault Address Register
b 4f
3:mrs x1, elr_el3 // Exception Link Register
mrs x2, spsr_el3 // Saved Processor Status Register 32bit
- mrs x3, fpsr // Floating point Status Register 32bit
mrs x4, esr_el3 // EL3 Exception syndrome register 32bit
mrs x5, far_el3 // EL3 Fault Address Register
+4:mrs x3, fpsr // Floating point Status Register 32bit
+
// Adjust SP to save next set
-4:add sp, sp, #FP_CONTEXT_SIZE
+ add sp, sp, #FP_CONTEXT_SIZE
// Push FP regs to Stack.
ALL_FP_REGS
@@ -357,22 +356,21 @@ ASM_PFX(CommonExceptionEntry): EL1_OR_EL2_OR_EL3(x6)
1:msr elr_el1, x1 // Exception Link Register
msr spsr_el1,x2 // Saved Processor Status Register 32bit
- msr fpsr, x3 // Floating point Status Register 32bit
msr esr_el1, x4 // EL1 Exception syndrome register 32bit
msr far_el1, x5 // EL1 Fault Address Register
b 4f
2:msr elr_el2, x1 // Exception Link Register
msr spsr_el2,x2 // Saved Processor Status Register 32bit
- msr fpsr, x3 // Floating point Status Register 32bit
msr esr_el2, x4 // EL2 Exception syndrome register 32bit
msr far_el2, x5 // EL2 Fault Address Register
b 4f
3:msr elr_el3, x1 // Exception Link Register
msr spsr_el3,x2 // Saved Processor Status Register 32bit
- msr fpsr, x3 // Floating point Status Register 32bit
msr esr_el3, x4 // EL3 Exception syndrome register 32bit
msr far_el3, x5 // EL3 Fault Address Register
-4:// pop all regs and return from exception.
+4:msr fpsr, x3 // Floating point Status Register 32bit
+
+ // pop all regs and return from exception.
sub sp, sp, #(FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)
ALL_GP_REGS
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