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authorLeendert van Doorn <leendert@paramecium.org>2016-03-24 15:30:05 -0500
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2016-03-25 07:09:49 +0100
commit7e5a6e394c65a295a761162621c546b1fea0b280 (patch)
tree2e23f635a7f63f54acdd8755514170bcf002447e /ArmPkg
parentda6ae666410e5b0354312e51c3e63775f79c33af (diff)
downloadedk2-platforms-7e5a6e394c65a295a761162621c546b1fea0b280.tar.xz
ArmPkg: apply Cortex-A57 errata
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'ArmPkg')
-rw-r--r--ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
index 135bd6b86d..3d39acd50c 100644
--- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
+++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
@@ -40,12 +40,15 @@ ArmCpuSetup (
}
//
- // If CPU is CortexA57 r0p0 apply Errata: 806969
+ // If CPU is CortexA57 r0p0 apply Errata workarounds
//
if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
- // DisableLoadStoreWB
- ArmSetCpuActlrBit (1ULL << 49);
+
+ // Errata 806969: DisableLoadStoreWB (1ULL << 49)
+ // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (1ULL << 44)
+ // Errata 814670: disable DMB nullification (1ULL << 58)
+ ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
}
}