ArmPkg/IndustryStandard/ArmStdSmc.h: Update Standard Service SMC Calls

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15747 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 94 insertions, 52 deletions

diff --git a/ArmPkg/Include/IndustryStandard/ArmSmc.h b/ArmPkg/Include/IndustryStandard/ArmSmc.h
deleted file mode 100644
index f6d062c713..0000000000
--- a/ArmPkg/Include/IndustryStandard/ArmSmc.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/** @file

-*

-*  Copyright (c) 2012-2013, ARM Limited. All rights reserved.

-*

-*  This program and the accompanying materials

-*  are licensed and made available under the terms and conditions of the BSD License

-*  which accompanies this distribution.  The full text of the license may be found at

-*  http://opensource.org/licenses/bsd-license.php

-*

-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-*

-**/

-

-#ifndef __ARM_SMC_H__

-#define __ARM_SMC_H__

-

-#include <IndustryStandard/ArmTrustZoneSmc.h>

-

-#define ARM_SMC_ID_PRESENCE       ARM_TRUSTZONE_ARM_FAST_SMC_ID_PRESENCE

-#define ARM_SMC_ID_UID            ARM_TRUSTZONE_ARM_FAST_SMC_ID_UID

-#define ARM_SMC_ID_REVISION       ARM_TRUSTZONE_ARM_FAST_SMC_ID_REVISION

-#define ARM_SMC_ARM_CPU_SUSPEND   0x80100001

-#define ARM_SMC_ARM_CPU_OFF       0x80100002

-#define ARM_SMC_ARM_CPU_ON        0x80100003

-#define ARM_SMC_ARM_MIGRATE       0x80100004

-

-#define ARM_SMC_ARM_CPU_SUSPEND_STANDBY_STATE       (0 << 16)

-#define ARM_SMC_ARM_CPU_SUSPEND_POWER_DOWN_STATE    (1 << 16)

-

-#define ARM_SMC_ARM_CPU_SUSPEND_CURRENT_CPU         (0 << 24)

-#define ARM_SMC_ARM_CPU_SUSPEND_CLUSTER_AFFINITY_1  (1 << 24)

-#define ARM_SMC_ARM_CPU_SUSPEND_CLUSTER_AFFINITY_2  (2 << 24)

-#define ARM_SMC_ARM_CPU_SUSPEND_CLUSTER_AFFINITY_3  (3 << 24)

-

-#define ARM_SMC_ARM_CPU_OFF_MASK_STATE              (1 << 16)

-#define ARM_SMC_ARM_CPU_OFF_STANDBY_STATE           (0 << 16)

-#define ARM_SMC_ARM_CPU_OFF_POWER_DOWN_STATE        (1 << 16)

-

-#define ARM_SMC_ARM_CPU_OFF_CURRENT_CPU             (0 << 24)

-#define ARM_SMC_ARM_CPU_OFF_CLUSTER_AFFINITY_1      (1 << 24)

-#define ARM_SMC_ARM_CPU_OFF_CLUSTER_AFFINITY_2      (2 << 24)

-#define ARM_SMC_ARM_CPU_OFF_CLUSTER_AFFINITY_3      (3 << 24)

-

-

-#define ARM_SMC_ARM_RETURN_SUCCESS            (UINTN)(0)

-#define ARM_SMC_ARM_RETURN_NOT_IMPLEMENTED    (UINTN)(-1)

-#define ARM_SMC_ARM_RETURN_INVALID_PARAMETER  (UINTN)(-2)

-#define ARM_SMC_ARM_RETURN_DENIED             (UINTN)(-3)

-#define ARM_SMC_ARM_RETURN_CORE_NOT_AVAILABLE (UINTN)(-3)

-

-#endif

diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
new file mode 100644
index 0000000000..720a6021ba
--- /dev/null
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -0,0 +1,94 @@
+/** @file

+*

+*  Copyright (c) 2012-2014, ARM Limited. All rights reserved.

+*

+*  This program and the accompanying materials

+*  are licensed and made available under the terms and conditions of the BSD License

+*  which accompanies this distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+*

+**/

+

+#ifndef __ARM_STD_SMC_H__

+#define __ARM_STD_SMC_H__

+

+/*

+ * SMC function IDs for Standard Service queries

+ */

+

+#define ARM_SMC_ID_STD_CALL_COUNT     0x8400ff00

+#define ARM_SMC_ID_STD_UID            0x8400ff01

+/*                                    0x8400ff02 is reserved */

+#define ARM_SMC_ID_STD_REVISION       0x8400ff03

+

+/*

+ * The 'Standard Service Call UID' is supposed to return the Standard

+ * Service UUID. This is a 128-bit value.

+ */

+#define ARM_SMC_STD_UUID0       0x108d905b

+#define ARM_SMC_STD_UUID1       0x47e8f863

+#define ARM_SMC_STD_UUID2       0xfbc02dae

+#define ARM_SMC_STD_UUID3       0xe2f64156

+

+/*

+ * ARM Standard Service Calls revision numbers

+ * The current revision is:  0.1

+ */

+#define ARM_SMC_STD_REVISION_MAJOR    0x0

+#define ARM_SMC_STD_REVISION_MINOR    0x1

+

+/*

+ * Power State Coordination Interface (PSCI) calls cover a subset of the

+ * Standard Service Call range.

+ * The list below is not exhaustive.

+ */

+#define ARM_SMC_ID_PSCI_VERSION                0x84000000

+#define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64    0xc4000001

+#define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32    0x84000001

+#define ARM_SMC_ID_PSCI_CPU_OFF                0x84000002

+#define ARM_SMC_ID_PSCI_CPU_ON_AARCH64         0xc4000003

+#define ARM_SMC_ID_PSCI_CPU_ON_AARCH32         0x84000003

+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64  0xc4000004

+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32  0x84000004

+#define ARM_SMC_ID_PSCI_MIGRATE_AARCH64        0xc4000005

+#define ARM_SMC_ID_PSCI_MIGRATE_AARCH32        0x84000005

+

+/* The current PSCI version is:  0.2 */

+#define ARM_SMC_PSCI_VERSION_MAJOR  0

+#define ARM_SMC_PSCI_VERSION_MINOR  2

+#define ARM_SMC_PSCI_VERSION  \

+  ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)

+

+/* PSCI return error codes */

+#define ARM_SMC_PSCI_RET_SUCCESS            0

+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED      -1

+#define ARM_SMC_PSCI_RET_INVALID_PARAMS     -2

+#define ARM_SMC_PSCI_RET_DENIED             -3

+#define ARM_SMC_PSCI_RET_ALREADY_ON         -4

+#define ARM_SMC_PSCI_RET_ON_PENDING         -5

+#define ARM_SMC_PSCI_RET_INTERN_FAIL        -6

+#define ARM_SMC_PSCI_RET_NOT_PRESENT        -7

+#define ARM_SMC_PSCI_RET_DISABLED           -8

+

+#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \

+  ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))

+

+#define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \

+  ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))

+

+#define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId)  ((TargetId) & 0xFF)

+#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId)  (((TargetId) >> 8) & 0xFF)

+

+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0    0

+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1    1

+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2    2

+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3    3

+

+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON          0

+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF         1

+#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING  2

+

+#endif