diff options
| author | Eugene Cohen <eugene@hp.com> | 2014-07-09 11:14:36 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-07-09 11:14:36 +0000 |
| commit | ffb91edfd5eef02d0f7e0326bfa7023e8ea9bb6d (patch) | |
| tree | e415ac1d936aae09c640faca975d8ec8f189d1ae /ArmPkg | |
| parent | 28087ef09f3ade5072ce1505a8acc8aff85787cd (diff) | |
| download | edk2-platforms-ffb91edfd5eef02d0f7e0326bfa7023e8ea9bb6d.tar.xz | |
ArmPkg/ArmLib: Improved ArmConfigureMmu Performance
Data & Instruction Caches can be kept enabled while the new
translation table is filled.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15647 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index d64c188dc5..1a5d982022 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -238,18 +238,6 @@ ArmConfigureMmu ( ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
- ArmCleanInvalidateDataCache ();
- ArmInvalidateInstructionCache ();
-
- ArmDisableDataCache ();
- ArmDisableInstructionCache();
- // TLBs are also invalidated when calling ArmDisableMmu()
- ArmDisableMmu ();
-
- // Make sure nothing sneaked into the cache
- ArmCleanInvalidateDataCache ();
- ArmInvalidateInstructionCache ();
-
// By default, mark the translation table as belonging to a uncached region
TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
while (MemoryTable->Length != 0) {
@@ -277,6 +265,18 @@ ArmConfigureMmu ( return RETURN_UNSUPPORTED;
}
+ ArmCleanInvalidateDataCache ();
+ ArmInvalidateInstructionCache ();
+
+ ArmDisableDataCache ();
+ ArmDisableInstructionCache();
+ // TLBs are also invalidated when calling ArmDisableMmu()
+ ArmDisableMmu ();
+
+ // Make sure nothing sneaked into the cache
+ ArmCleanInvalidateDataCache ();
+ ArmInvalidateInstructionCache ();
+
ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
|