Armkg: Fix EDK2 coding style

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11734 6f19259b-4bc3-4df7-8a09-765794883524

6 files changed, 152 insertions, 134 deletions

diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c
index 7c59af7fef..17e463f97b 100644
--- a/ArmPkg/Drivers/CpuDxe/Exception.c
+++ b/ArmPkg/Drivers/CpuDxe/Exception.c
@@ -144,60 +144,60 @@ InitializeExceptions (
   ArmDisableFiq ();

 

   if (FeaturePcdGet(PcdRelocateVectorTable) == TRUE) {

-      //

-      // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress.

-      //

-      Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;

-    

-      //

-      // Reserve space for the exception handlers

-      //

-      Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);

-      VectorBase = (UINT32 *)(UINTN)Base;

-      Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);

-      // If the request was for memory that's not in the memory map (which is often the case for 0x00000000

-      // on embedded systems, for example, we don't want to hang up.  So we'll check here for a status of 

-      // EFI_NOT_FOUND, and continue in that case.

-      if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {

-        ASSERT_EFI_ERROR (Status);

-      }

-    

+    //

+    // Copy an implementation of the ARM exception vectors to PcdCpuVectorBaseAddress.

+    //

+    Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;

+

+    //

+    // Reserve space for the exception handlers

+    //

+    Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);

+    VectorBase = (UINT32 *)(UINTN)Base;

+    Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);

+    // If the request was for memory that's not in the memory map (which is often the case for 0x00000000

+    // on embedded systems, for example, we don't want to hang up.  So we'll check here for a status of

+    // EFI_NOT_FOUND, and continue in that case.

+    if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {

+      ASSERT_EFI_ERROR (Status);

+    }

+

     if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {

       // Save existing vector table, in case debugger is already hooked in

       CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (gDebuggerExceptionHandlers));

     }

-    

-      // Copy our assembly code into the page that contains the exception vectors. 

-      CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);

-    

-      //

-      // Patch in the common Assembly exception handler

-      //

-      Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;

-      *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;

-    

-      //

-      // Initialize the C entry points for interrupts

-      //

-      for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {

+

+    // Copy our assembly code into the page that contains the exception vectors.

+    CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);

+

+    //

+    // Patch in the common Assembly exception handler

+    //

+    Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;

+    *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;

+

+    //

+    // Initialize the C entry points for interrupts

+    //

+    for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {

       if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||

           (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)(UINTN)0xEAFFFFFE)) {

-          // Exception handler contains branch to vector location (jmp $) so no handler

-          // NOTE: This code assumes vectors are ARM and not Thumb code

-          Status = RegisterInterruptHandler (Index, NULL);

-          ASSERT_EFI_ERROR (Status);

-        } else {

-          // If the debugger has alread hooked put its vector back

-          VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];

-        }

+        // Exception handler contains branch to vector location (jmp $) so no handler

+        // NOTE: This code assumes vectors are ARM and not Thumb code

+        Status = RegisterInterruptHandler (Index, NULL);

+        ASSERT_EFI_ERROR (Status);

+      } else {

+        // If the debugger has already hooked put its vector back

+        VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];

       }

-    

-      // Flush Caches since we updated executable stuff

-      InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);

+    }

+

+    // Flush Caches since we updated executable stuff

+    InvalidateInstructionCacheRange ((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);

 

-      //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.

-      //      The Vector Base Address Register defines the location

-      ArmWriteVBar(PcdGet32(PcdCpuVectorBaseAddress));

+    //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.

+    //      The Vector Base Address Register defines the location

+    ArmWriteVBar(PcdGet32(PcdCpuVectorBaseAddress));

   } else {

     // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.

     ArmWriteVBar((UINT32)ExceptionHandlersStart);

diff --git a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
index 6cc6cc6193..ea03097ef2 100644
--- a/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
+++ b/ArmPkg/Drivers/PL310L2Cache/PL310L2Cache.c
@@ -22,66 +22,71 @@
 #define L2x0ReadReg(reg)                    MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)

 

 // Initialize PL320 L2 Cache Controller

-VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {

-    UINT32 Data;

-    UINT32 Revision;

-    UINT32 Aux;

-    UINT32 PfCtl;

-    UINT32 PwrCtl;

-

-    // Check if L2x0 is present and is an ARM implementation

-    Data = L2x0ReadReg(L2X0_CACHEID);

-    if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {

-        ASSERT(0);

-        return;

-    }

-

-    // Check if L2x0 is PL310

-    if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {

-        ASSERT(0);

-        return;

-    }

-

-    // RTL release

-    Revision = Data & 0x3F;

-

-    // Check if L2x0 is already enabled then we disable it

-    Data = L2x0ReadReg(L2X0_CTRL);

-    if (Data & L2X0_CTRL_ENABLED) {

-        L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);

-    }

-

-    //

-    // Set up global configurations

-    //

-

-    // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO

-    Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;

-    // Use AWCACHE attributes for WA

-    Aux |= L2x0_AUXCTRL_AW_AWCACHE;

-    // Use default Size

-    Data = L2x0ReadReg(L2X0_AUXCTRL);

-    Aux |= Data & (0x7 << 17);

-    // Use default associativity

-    Aux |= Data & (0x1 << 16);

-    // Enabled I & D Prefetch

-    Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;

-    

-    if (Revision >= 5) {

-        // Prefetch Offset Register

-        PfCtl = L2x0ReadReg(L2X0_PFCTRL);

-        // - Prefetch increment set to 0

-        // - Prefetch dropping off

-        // - Double linefills off

-        L2x0WriteReg(L2X0_PFCTRL, PfCtl);

-

-        // Power Control Register - L2X0_PWRCTRL

-        PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);

-        // - Standby when idle off

-        // - Dynamic clock gating off

-        // - Nc,NC-shared dropping off

-        L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);

-    }

+VOID

+L2x0CacheInit (

+  IN  UINTN   L2x0Base,

+  IN  BOOLEAN CacheEnabled

+  )

+{

+  UINT32 Data;

+  UINT32 Revision;

+  UINT32 Aux;

+  UINT32 PfCtl;

+  UINT32 PwrCtl;

+

+  // Check if L2x0 is present and is an ARM implementation

+  Data = L2x0ReadReg(L2X0_CACHEID);

+  if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {

+    ASSERT(0);

+    return;

+  }

+

+  // Check if L2x0 is PL310

+  if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {

+    ASSERT(0);

+    return;

+  }

+

+  // RTL release

+  Revision = Data & 0x3F;

+

+  // Check if L2x0 is already enabled then we disable it

+  Data = L2x0ReadReg(L2X0_CTRL);

+  if (Data & L2X0_CTRL_ENABLED) {

+    L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);

+  }

+

+  //

+  // Set up global configurations

+  //

+

+  // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO

+  Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;

+  // Use AWCACHE attributes for WA

+  Aux |= L2x0_AUXCTRL_AW_AWCACHE;

+  // Use default Size

+  Data = L2x0ReadReg(L2X0_AUXCTRL);

+  Aux |= Data & (0x7 << 17);

+  // Use default associativity

+  Aux |= Data & (0x1 << 16);

+  // Enabled I & D Prefetch

+  Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;

+

+  if (Revision >= 5) {

+    // Prefetch Offset Register

+    PfCtl = L2x0ReadReg(L2X0_PFCTRL);

+    // - Prefetch increment set to 0

+    // - Prefetch dropping off

+    // - Double linefills off

+    L2x0WriteReg(L2X0_PFCTRL, PfCtl);

+

+    // Power Control Register - L2X0_PWRCTRL

+    PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);

+    // - Standby when idle off

+    // - Dynamic clock gating off

+    // - Nc,NC-shared dropping off

+    L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);

+  }

 

     if (Revision >= 4) {

         // Tag RAM Latency register

@@ -107,24 +112,24 @@ VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {
                | L2_DATA_ACCESS_LATENCY;

     }

 

-    // Write Auxiliary value

-    L2x0WriteReg(L2X0_AUXCTRL, Aux);

+  // Write Auxiliary value

+  L2x0WriteReg(L2X0_AUXCTRL, Aux);

 

-    //

-    // Invalidate all entries in cache

-    //

-    L2x0WriteReg(L2X0_INVWAY, 0xffff);

-    // Poll cache maintenance register until invalidate operation is complete

-    while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);

+  //

+  // Invalidate all entries in cache

+  //

+  L2x0WriteReg(L2X0_INVWAY, 0xffff);

+  // Poll cache maintenance register until invalidate operation is complete

+  while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);

 

-    // Write to the Lockdown D and Lockdown I Register 9 if required

-    // - Not required

+  // Write to the Lockdown D and Lockdown I Register 9 if required

+  // - Not required

 

-    // Clear any residual raw interrupts

-    L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);

+  // Clear any residual raw interrupts

+  L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);

 

-    // Enable the cache

-    if (CacheEnabled) {

-        L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);

-    }

+  // Enable the cache

+  if (CacheEnabled) {

+    L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);

+  }

 }

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c
index 65c09a1a35..929140774c 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCore.c
@@ -50,8 +50,8 @@ ArmInvalidScu (
 
     scu_base = ArmGetScuBaseAddress();
 
-    /* Invalidate all: write -1 to SCU Invalidate All register */
+    // Invalidate all: write -1 to SCU Invalidate All register
     MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff);
-    /* Enable SCU */
+    // Enable SCU
     MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1);
 }
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 7dbbaf7d0f..5b12d1dee2 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -295,21 +295,21 @@ ASM_PFX(ArmWriteCPACR):
   bx      lr
 
 ASM_PFX(ArmEnableVFP):
-  // Enable VFP registers
+  # Enable VFP registers
   mrc     p15, 0, r0, c1, c0, 2
-  orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
+  orr     r0, r0, #0x00f00000   @ Enable VPF access (V* instructions)
   mcr     p15, 0, r0, c1, c0, 2
-  mov     r0, #0x40000000       // Set EN bit in FPEXC
-  mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
+  mov     r0, #0x40000000       @ Set EN bit in FPEXC
+  mcr     p10,#0x7,r0,c8,c0,#0  @ msr     FPEXC,r0 in ARM assembly
   bx      lr
 
 ASM_PFX(ArmCallWFI):
   wfi
   bx      lr
 
-//Note: Return 0 in Uniprocessor implementation
+#Note: Return 0 in Uniprocessor implementation
 ASM_PFX(ArmReadCbar):
-  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
+  mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
   bx      lr
 
 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
diff --git a/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c b/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
index c7a9341e86..28edd674c0 100644
--- a/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
+++ b/ArmPkg/Library/ArmMPCoreMailBoxLib/ArmMPCoreMailBox.c
@@ -16,10 +16,18 @@
 #include <Library/PcdLib.h>

 #include <Library/IoLib.h>

 

-VOID ArmClearMPCoreMailbox() {

+VOID

+ArmClearMPCoreMailbox (

+  VOID

+  )

+{

   MmioWrite32(PcdGet32(PcdMPCoreMailboxClearAddress),PcdGet32(PcdMPCoreMailboxClearValue));

 }

 

-UINTN ArmGetMPCoreMailbox() {

-    return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress));

+UINTN

+ArmGetMPCoreMailbox (

+  VOID

+  )

+{

+  return MmioRead32(PcdGet32(PcdMPCoreMailboxGetAddress));

 }

diff --git a/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c b/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
index b7d79c3c6e..6193cb6132 100644
--- a/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
+++ b/ArmPkg/Library/L2X0CacheLibNull/L2X0Cache.c
@@ -15,6 +15,11 @@
 #include <Library/L2X0CacheLib.h>

 

 // Initialize L2X0 Cache Controller

-VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled) {

+VOID

+L2x0CacheInit (

+  IN  UINTN   L2x0Base,

+  IN  BOOLEAN CacheEnabled

+  )

+{

     //No implementation

 }