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authorBrendan Jackman <brendan.jackman@arm.com>2014-05-08 14:59:04 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2014-05-08 14:59:04 +0000
commit73ca50096eea3edc64e2c635b6b6d99fbb5572d5 (patch)
treec2005188cc6c82478ff1a1e0e3c101297e64d53e /ArmPkg
parent7eb1d8522a583b2a0a8eea5034be7b30ab14e0f8 (diff)
downloadedk2-platforms-73ca50096eea3edc64e2c635b6b6d99fbb5572d5.tar.xz
ARM Packages: Use AND instead of BIC instruction with immediate
AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/AArch64Support.S13
1 files changed, 6 insertions, 7 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index a57e976979..76007505f3 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -146,7 +146,7 @@ ASM_PFX(ArmDisableMmu):
2: mrs x0, sctlr_el2 // Read System Control Register EL2
b 4f
3: mrs x0, sctlr_el3 // Read System Control Register EL3
-4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
+4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back
tlbi vmalle1
@@ -168,9 +168,8 @@ ASM_PFX(ArmDisableCachesAndMmu):
2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_M_BIT // Disable MMU
- bic x0, x0, #CTRL_C_BIT // Disable D Cache
- bic x0, x0, #CTRL_I_BIT // Disable I Cache
+4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches
+ and x0, x0, x1
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
@@ -219,7 +218,7 @@ ASM_PFX(ArmDisableDataCache):
2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_C_BIT // Clear C bit
+4: and x0, x0, #~CTRL_C_BIT // Clear C bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
@@ -257,7 +256,7 @@ ASM_PFX(ArmDisableInstructionCache):
2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_I_BIT // Clear I bit
+4: and x0, x0, #~CTRL_I_BIT // Clear I bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f
@@ -291,7 +290,7 @@ ASM_PFX(ArmDisableAlignmentCheck):
2: mrs x0, sctlr_el2 // Get control register EL2
b 4f
3: mrs x0, sctlr_el3 // Get control register EL3
-4: bic x0, x0, #CTRL_A_BIT // Clear A (alignment check) bit
+4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit
EL1_OR_EL2_OR_EL3(x1)
1: msr sctlr_el1, x0 // Write back control register
b 4f