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authorBrendan Jackman <brendan.jackman@arm.com>2014-05-08 14:57:51 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2014-05-08 14:57:51 +0000
commit7eb1d8522a583b2a0a8eea5034be7b30ab14e0f8 (patch)
tree5a0756a6bcda4376a297e509a12ccf61c9a94604 /ArmPkg
parent0db208eacaf2727262e91b0c13b21300f203500f (diff)
downloadedk2-platforms-7eb1d8522a583b2a0a8eea5034be7b30ab14e0f8.tar.xz
ArmPkg/CpuDxe/AArch64: use STUR instruction for signed offset
The AARCH64 LDR and STR instructions only support signed offsets for post- and pre-indexed addressing. For normal signed offset addressing, the mnemonic is STUR. GNU As automatically assembles STR with signed offset as STUR, but Clang's integrated assembler doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15508 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
-rw-r--r--ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
index d6eefc43c7..42e3596280 100644
--- a/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
+++ b/ArmPkg/Drivers/CpuDxe/AArch64/ExceptionSupport.S
@@ -241,8 +241,8 @@ ASM_PFX(SErrorA32):
#undef REG_PAIR
#undef REG_ONE
-#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
-#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) str REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
+#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) stp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
+#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) stur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
ASM_PFX(SynchronousExceptionEntry):
// Move the stackpointer so we can reach our structure with the str instruction.
@@ -355,9 +355,9 @@ ASM_PFX(AsmCommonExceptionEntry):
#undef REG_PAIR
#undef REG_ONE
-#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) ldp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
+#define REG_PAIR(REG1, REG2, OFFSET, CONTEXT_SIZE) ldp REG1, REG2, [sp, #(OFFSET-CONTEXT_SIZE)]
-#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) ldr REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
+#define REG_ONE(REG1, OFFSET, CONTEXT_SIZE) ldur REG1, [sp, #(OFFSET-CONTEXT_SIZE)]
// Adjust SP to pop system registers
add sp, sp, #(GP_CONTEXT_SIZE + FP_CONTEXT_SIZE + SYS_CONTEXT_SIZE)