ArmPlatformPkg: Add support for ARM RTSM Versatile Express A15x1 and A15x4

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12456 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 150 insertions, 2 deletions

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
index c6c507b753..5e1e465630 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
@@ -34,7 +34,9 @@
 

 [Sources.common]

   RTSM.c

-  RTSMMem.c

+  RTSMMem.c  

+  RTSMHelper.asm    | RVCT

+  RTSMHelper.S      | GCC

 

 [FeaturePcd]

   gEmbeddedTokenSpaceGuid.PcdCacheEnable

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressSecLib.inf
index eb2f70956a..bf6caadcee 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressSecLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressSecLib.inf
@@ -36,6 +36,8 @@
   RTSM.c
   RTSMBoot.asm     | RVCT
   RTSMBoot.S       | GCC
+  RTSMHelper.asm   | RVCT
+  RTSMHelper.S     | GCC
 
 [Protocols]
 
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
index 5741915b69..a8674acf7c 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
@@ -148,7 +148,7 @@ PrePeiCoreGetMpCoreInfo (
   UINT32   ProcType;
 
   ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
-  if (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) {
+  if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
     // Only support one cluster
     *CoreCount    = ArmGetCpuCountPerCluster ();
     *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.S
new file mode 100644
index 0000000000..949e7a3014
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.S
@@ -0,0 +1,71 @@
+#

+#  Copyright (c) 2011, ARM Limited. All rights reserved.

+#  

+#  This program and the accompanying materials                          

+#  are licensed and made available under the terms and conditions of the BSD License         

+#  which accompanies this distribution.  The full text of the license may be found at        

+#  http:#opensource.org/licenses/bsd-license.php                                            

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+#

+#

+

+#include <AsmMacroIoLib.h>

+#include <Base.h>

+#include <Library/PcdLib.h>

+#include <AutoGen.h>

+#.include AsmMacroIoLib.inc

+

+#include <Chipset/ArmCortexA9.h>

+

+.text

+.align 2

+

+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)

+

+# IN None

+# OUT r0 = SCU Base Address

+ASM_PFX(ArmGetScuBaseAddress):

+  # Read Configuration Base Address Register. ArmCBar cannot be called to get

+  # the Configuration BAR as a stack is not necessary setup. The SCU is at the

+  # offset 0x0000 from the Private Memory Region.

+  mrc   p15, 4, r0, c15, c0, 0

+  bx  lr

+

+# IN None

+# OUT r0 = number of cores present in the system

+ASM_PFX(ArmGetCpuCountPerCluster):

+  stmfd SP!, {r1-r2}

+

+  # Read CP15 MIDR

+  mrc   p15, 0, r1, c0, c0, 0

+

+  # Check if the CPU is A15

+  mov   r1, r1, LSR #4

+  LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)

+  and   r1, r1, r0

+

+  LoadConstantToReg (ARM_CPU_TYPE_A15, r0)

+  cmp   r1, r0

+  beq   _Read_cp15_reg

+

+_CPU_is_not_A15:

+  mov   r2, lr                           @ Save link register

+  bl    ArmGetScuBaseAddress             @ Read SCU Base Address

+  mov   lr, r2                           @ Restore link register val

+  ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     @ Read SCU Config reg to get CPU count

+  b     _Return

+

+_Read_cp15_reg:

+  mrc   p15, 1, r0, c9, c0, 2            @ Read C9 register of CP15 to get CPU count

+  lsr   r0, #24

+

+_Return:

+  and   r0, r0, #3

+  # Add '1' to the number of CPU on the Cluster

+  add   r0, r0, #1

+  ldmfd SP!, {r1-r2}

+  bx lr

+

+ASM_FUNCTION_REMOVE_IF_UNREFERENCED 

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.asm
new file mode 100644
index 0000000000..7326237bc7
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMHelper.asm
@@ -0,0 +1,73 @@
+//

+//  Copyright (c) 2011, ARM Limited. All rights reserved.

+//  

+//  This program and the accompanying materials                          

+//  are licensed and made available under the terms and conditions of the BSD License         

+//  which accompanies this distribution.  The full text of the license may be found at        

+//  http://opensource.org/licenses/bsd-license.php                                            

+//

+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+//

+//

+

+#include <AsmMacroIoLib.h>

+#include <Base.h>

+#include <Library/PcdLib.h>

+

+#include <Chipset/ArmCortexA9.h>

+

+#include <AutoGen.h>

+

+  INCLUDE AsmMacroIoLib.inc

+

+  EXPORT    ArmGetCpuCountPerCluster

+    

+  AREA RTSMHelper, CODE, READONLY

+

+// IN None

+// OUT r0 = SCU Base Address

+ArmGetScuBaseAddress

+  // Read Configuration Base Address Register. ArmCBar cannot be called to get

+  // the Configuration BAR as a stack is not necessary setup. The SCU is at the

+  // offset 0x0000 from the Private Memory Region.

+  mrc   p15, 4, r0, c15, c0, 0

+  bx  lr

+

+// IN None

+// OUT r0 = number of cores present in the system

+ArmGetCpuCountPerCluster

+  stmfd SP!, {r1-r2}

+

+  // Read CP15 MIDR

+  mrc   p15, 0, r1, c0, c0, 0

+

+  // Check if the CPU is A15

+  mov   r1, r1, LSR #4

+  mov   r0, #ARM_CPU_TYPE_MASK

+  and   r1, r1, r0

+

+  mov   r0, #ARM_CPU_TYPE_A15

+  cmp   r1, r0

+  beq   _Read_cp15_reg

+

+_CPU_is_not_A15

+  mov   r2, lr                              ; Save link register

+  bl    ArmGetScuBaseAddress                ; Read SCU Base Address

+  mov   lr, r2                              ; Restore link register val

+  ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     ; Read SCU Config reg to get CPU count

+  b     _Return

+

+_Read_cp15_reg

+  mrc   p15, 1, r0, c9, c0, 2            ; Read C9 register of CP15 to get CPU count

+  lsr   r0, #24

+

+

+_Return

+  and   r0, r0, #3

+  // Add '1' to the number of CPU on the Cluster

+  add   r0, r0, #1

+  ldmfd SP!, {r1-r2}

+  bx lr

+

+  END