ArmPlatformPkg: Added support for Aarch64 AEM RTSM model

    
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>




git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14490 6f19259b-4bc3-4df7-8a09-765794883524

6 files changed, 197 insertions, 17 deletions

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelper.S
new file mode 100644
index 0000000000..50703ec275
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelper.S
@@ -0,0 +1,71 @@
+#

+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

+#

+#  This program and the accompanying materials

+#  are licensed and made available under the terms and conditions of the BSD License

+#  which accompanies this distribution.  The full text of the license may be found at

+#  http://opensource.org/licenses/bsd-license.php

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+#

+#

+

+#include <AsmMacroIoLibV8.h>

+#include <Base.h>

+#include <Library/ArmLib.h>

+#include <Library/PcdLib.h>

+#include <AutoGen.h>

+

+.text

+.align 2

+

+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)

+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)

+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)

+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)

+

+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)

+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)

+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)

+

+ASM_PFX(ArmPlatformPeiBootAction):

+  ret

+

+# IN None

+# OUT x0 = number of cores present in the system

+ASM_PFX(ArmGetCpuCountPerCluster):

+  LoadConstantToReg (_gPcd_FixedAtBuild_PcdCoreCount, x0)

+  ldrh  w0, [x0]

+  ret

+

+//UINTN

+//ArmPlatformIsPrimaryCore (

+//  IN UINTN MpId

+//  );

+ASM_PFX(ArmPlatformIsPrimaryCore):

+  LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)

+  ldrh  w1, [x1]

+  and   x0, x0, x1

+  LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x1)

+  ldrh  w1, [x1]

+  cmp   w0, w1

+  b.ne  1f

+  mov	x0, #1

+  ret

+1:

+  mov	x0, #0

+  ret

+

+//UINTN

+//ArmPlatformGetCorePosition (

+//  IN UINTN MpId

+//  );

+// With this function: CorePos = (ClusterId * 4) + CoreId

+ASM_PFX(ArmPlatformGetCorePosition):

+  and   x1, x0, #ARM_CORE_MASK

+  and   x0, x0, #ARM_CLUSTER_MASK

+  add   x0, x1, x0, LSR #6

+  ret

+

+ASM_FUNCTION_REMOVE_IF_UNREFERENCED

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
index d4c1093bab..0cf605bbd0 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
@@ -1,5 +1,5 @@
 #/* @file

-#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

+#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

 #  

 #  This program and the accompanying materials                          

 #  are licensed and made available under the terms and conditions of the BSD License         

@@ -40,6 +40,9 @@
   Arm/RTSMHelper.asm    | RVCT

   Arm/RTSMHelper.S      | GCC

 

+[Sources.AARCH64]

+  AArch64/RTSMHelper.S  | GCC

+

 [FeaturePcd]

   gEmbeddedTokenSpaceGuid.PcdCacheEnable

   gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping

@@ -52,3 +55,5 @@
 

   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

   gArmTokenSpaceGuid.PcdArmPrimaryCore

+ 

+  gArmPlatformTokenSpaceGuid.PcdCoreCount

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
index 53252b1d05..7cb666f79f 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
@@ -38,6 +38,9 @@
   Arm/RTSMHelper.asm    | RVCT

   Arm/RTSMHelper.S      | GCC

 

+[Sources.AARCH64]

+  AArch64/RTSMHelper.S  | GCC

+

 [FeaturePcd]

   gEmbeddedTokenSpaceGuid.PcdCacheEnable

   gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping

@@ -50,3 +53,5 @@
 

   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

   gArmTokenSpaceGuid.PcdArmPrimaryCore

+

+  gArmPlatformTokenSpaceGuid.PcdCoreCount

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
index 5cafda8365..ea73f62956 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c
@@ -1,14 +1,14 @@
 /** @file

 *

-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.

-*  

-*  This program and the accompanying materials                          

-*  are licensed and made available under the terms and conditions of the BSD License         

-*  which accompanies this distribution.  The full text of the license may be found at        

-*  http://opensource.org/licenses/bsd-license.php                                            

+*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

 *

-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+*  This program and the accompanying materials

+*  are licensed and made available under the terms and conditions of the BSD License

+*  which accompanies this distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 *

 **/

 

@@ -66,6 +66,46 @@ ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,

     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,

     (UINT64)0xFFFFFFFF

+  },

+  {

+    // Cluster 1, Core 0

+    0x1, 0x0,

+

+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,

+    (UINT64)0xFFFFFFFF

+  },

+  {

+    // Cluster 1, Core 1

+    0x1, 0x1,

+

+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,

+    (UINT64)0xFFFFFFFF

+  },

+  {

+    // Cluster 1, Core 2

+    0x1, 0x2,

+

+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,

+    (UINT64)0xFFFFFFFF

+  },

+  {

+    // Cluster 1, Core 3

+    0x1, 0x3,

+

+    // MP Core MailBox Set/Get/Clear Addresses and Clear Value

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,

+    (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,

+    (UINT64)0xFFFFFFFF

   }

 };

 

@@ -131,7 +171,7 @@ PrePeiCoreGetMpCoreInfo (
 

   ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;

   if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {

-    // Only support one cluster

+    // Only support one cluster on all but ARMv8 FVP platform. FVP still uses CortexA9 ID.

     *CoreCount    = ArmGetCpuCountPerCluster ();

     *ArmCoreTable = mVersatileExpressMpCoreInfoTable;

     return EFI_SUCCESS;

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/RTSMBoot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/RTSMBoot.S
new file mode 100644
index 0000000000..ded8a3162b
--- /dev/null
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/RTSMBoot.S
@@ -0,0 +1,64 @@
+//

+//  Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.

+//

+//  This program and the accompanying materials

+//  are licensed and made available under the terms and conditions of the BSD License

+//  which accompanies this distribution.  The full text of the license may be found at

+//  http://opensource.org/licenses/bsd-license.php

+//

+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+//

+//

+

+#include <AsmMacroIoLib.h>

+#include <Base.h>

+#include <Library/ArmPlatformLib.h>

+#include <AutoGen.h>

+#include <ArmPlatform.h>

+

+.text

+.align 3

+

+GCC_ASM_EXPORT(ArmPlatformSecBootAction)

+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)

+GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite)

+GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead)

+

+/**

+  Call at the beginning of the platform boot up

+

+  This function allows the firmware platform to do extra actions at the early

+  stage of the platform power up.

+

+  Note: This function must be implemented in assembler as there is no stack set up yet

+

+**/

+ASM_PFX(ArmPlatformSecBootAction):

+  ret

+

+/**

+  Initialize the memory where the initial stacks will reside

+

+  This memory can contain the initial stacks (Secure and Secure Monitor stacks).

+  In some platform, this region is already initialized and the implementation of this function can

+  do nothing. This memory can also represent the Secure RAM.

+  This function is called before the satck has been set up. Its implementation must ensure the stack

+  pointer is not used (probably required to use assembly language)

+

+**/

+ASM_PFX(ArmPlatformSecBootMemoryInit):

+  // The SMC does not need to be initialized for RTSM

+  ret

+

+/* Write the flag register used to start Secondary cores */

+ASM_PFX(ArmSecMpCoreSecondariesWrite):

+  // Write to the CPU Mailbox

+  ret

+

+/* Read the flag register used to start Secondary cores */

+ASM_PFX(ArmSecMpCoreSecondariesRead):

+  // Return the value from the CPU Mailbox

+  mov x0, #0

+  ret

+

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf
index f1e29ff01b..27c78f42d8 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf
@@ -38,13 +38,8 @@
   Arm/RTSMBoot.asm     | RVCT

   Arm/RTSMBoot.S       | GCC

 

-[FeaturePcd]

-  gEmbeddedTokenSpaceGuid.PcdCacheEnable

-  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping

-  gArmPlatformTokenSpaceGuid.PcdStandalone

+[Sources.AARCH64]

+  AArch64/RTSMBoot.S   | GCC

 

 [FixedPcd]

   gArmTokenSpaceGuid.PcdFvBaseAddress

-

-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

-  gArmTokenSpaceGuid.PcdArmPrimaryCore