ArmPlatformPkg/ArmVExpressPkg: Introduce the PcdNorFlashRemapping feature PCD

Platform designers can decide to not remap the DRAM at 0x0 on the VExpress motherboard.
This PCD can be used to set this feature.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11807 6f19259b-4bc3-4df7-8a09-765794883524

4 files changed, 109 insertions, 82 deletions

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
index 80631240a7..a6186b5e7e 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
@@ -44,6 +44,7 @@
 [FeaturePcd]
   gEmbeddedTokenSpaceGuid.PcdCacheEnable
   gArmPlatformTokenSpaceGuid.PcdStandalone
+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
 
 [FixedPcd]
   gArmTokenSpaceGuid.PcdNormalFdBaseAddress
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
index a9b2221304..c0af6940c5 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
@@ -45,6 +45,7 @@
 [FeaturePcd]

   gEmbeddedTokenSpaceGuid.PcdCacheEnable

   gArmPlatformTokenSpaceGuid.PcdStandalone

+  gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping

 

 [FixedPcd]

   gArmTokenSpaceGuid.PcdNormalFdBaseAddress

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
index 3acb713f3a..8f6c2b0f4f 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c
@@ -178,10 +178,15 @@ ArmPlatformBootRemapping (
   VOID
   )
 {
-    UINT32 val32  = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
-    // we remap the DRAM to 0x0
-    MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (val32 & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
-}
+  UINT32 Value;
+
+  if (FeaturePcdGet(PcdNorFlashRemapping)) {
+    SerialPrint ("Secure ROM at 0x0\n\r");
+  } else {
+    Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
+    // Remap the DRAM to 0x0
+    MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
+  }
 
 /**
   Initialize controllers that must setup at the early stage
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
index cd72f4af3c..eed01ed7ef 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c
@@ -18,6 +18,9 @@
 #include <Library/IoLib.h>

 #include <Library/MemoryAllocationLib.h>

 

+// Number of Virtual Memory Map Descriptors without a Logic Tile

+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6

+

 // DDR attributes

 #define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK

 #define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED

@@ -34,90 +37,107 @@
                                     entry

 

 **/

-VOID ArmPlatformGetVirtualMemoryMap(ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap) {

-    UINT32                        val32;

-    UINT32                        CacheAttributes;

-    BOOLEAN                       bTrustzoneSupport;

-    UINTN                         Index = 0;

-    ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;

-

-    ASSERT(VirtualMemoryMap != NULL);

-

-    VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * 9);

-    if (VirtualMemoryTable == NULL) {

-        return;

-    }

-

-    // Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.

-    // As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case

-    val32 = MmioRead32(ARM_VE_SYS_CFGRW1_REG);

-    if (ARM_VE_CFGRW1_TZASC_EN_BIT_MASK & val32) {

-        bTrustzoneSupport = TRUE;

-    } else {

-        bTrustzoneSupport = FALSE;

-    }

-

+VOID

+ArmPlatformGetVirtualMemoryMap (

+  IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap

+  )

+{

+  ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;

+  BOOLEAN                       bTrustzoneSupport;

+  UINTN                         Index = 0;

+  ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;

+

+  ASSERT(VirtualMemoryMap != NULL);

+

+  VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));

+  if (VirtualMemoryTable == NULL) {

+      return;

+  }

+

+  // Check if SMC TZASC is enabled. If Trustzone not enabled then all the entries remain in Secure World.

+  // As this value can be changed in the Board Configuration file, the UEFI firmware needs to work for both case

+  if (ArmPlatformTrustzoneSupported ()) {

+    bTrustzoneSupport = TRUE;

+  } else {

+      bTrustzoneSupport = FALSE;

+  }

+

+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {

+      CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);

+  } else {

+      CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);

+  }

+

+  // ReMap (Either NOR Flash or DRAM)

+  VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;

+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;

+  VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;

+

+  if (FeaturePcdGet(PcdNorFlashRemapping)) {

+    // Map the NOR Flash as Secure Memory

     if (FeaturePcdGet(PcdCacheEnable) == TRUE) {

-        CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_CACHED : DDR_ATTRIBUTES_SECURE_CACHED);

+      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_SECURE_CACHED;

     } else {

-        CacheAttributes = (bTrustzoneSupport ? DDR_ATTRIBUTES_UNCACHED : DDR_ATTRIBUTES_SECURE_UNCACHED);

-    }

-

-    // ReMap (Either NOR Flash or DRAM)

-    VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;

-    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;

-    VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;

-    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

-

-    // DDR

-    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;

-    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;

-    VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;

-    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

-

-    // SMC CS7

-    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;

-    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;

-    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;

-    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

-

-    // SMB CS0-CS1 - NOR Flash 1 & 2

-    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;

-    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;

-    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;

-    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

-

-    // SMB CS2 - SRAM

-    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;

-    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;

-    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;

-    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;

-

-    // SMB CS3-CS6 - Motherboard Peripherals

-    VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;

-    VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;

-    VirtualMemoryTable[Index].Length       = ARM_VE_SMB_PERIPH_SZ;

-    VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

-

-    // If a Logic Tile is connected to The ARM Versatile Express Motherboard

-    if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {

-        VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;

-        VirtualMemoryTable[Index].VirtualBase  = ARM_VE_EXT_AXI_BASE;

-        VirtualMemoryTable[Index].Length       = ARM_VE_EXT_AXI_SZ;

-        VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

+      VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_SECURE_UNCACHED;

     }

-

-    // End of Table

-    VirtualMemoryTable[++Index].PhysicalBase = 0;

-    VirtualMemoryTable[Index].VirtualBase  = 0;

-    VirtualMemoryTable[Index].Length       = 0;

-    VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

-

-    *VirtualMemoryMap = VirtualMemoryTable;

+  } else {

+    // DRAM mapping

+    VirtualMemoryTable[Index].Attributes   = CacheAttributes;

+  }

+

+  // DDR

+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;

+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;

+  VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;

+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;

+

+  // SMC CS7

+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;

+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE;

+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ;

+  VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

+

+  // SMB CS0-CS1 - NOR Flash 1 & 2

+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;

+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;

+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;

+  VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

+

+  // SMB CS2 - SRAM

+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;

+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;

+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;

+  VirtualMemoryTable[Index].Attributes   = CacheAttributes;

+

+  // SMB CS3-CS6 - Motherboard Peripherals

+  VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;

+  VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;

+  VirtualMemoryTable[Index].Length       = ARM_VE_SMB_PERIPH_SZ;

+  VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

+

+  // If a Logic Tile is connected to The ARM Versatile Express Motherboard

+  if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {

+      VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;

+      VirtualMemoryTable[Index].VirtualBase  = ARM_VE_EXT_AXI_BASE;

+      VirtualMemoryTable[Index].Length       = ARM_VE_EXT_AXI_SZ;

+      VirtualMemoryTable[Index].Attributes   = (bTrustzoneSupport ? ARM_MEMORY_REGION_ATTRIBUTE_DEVICE : ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE);

+

+      ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));

+  } else {

+    ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);

+  }

+

+  // End of Table

+  VirtualMemoryTable[++Index].PhysicalBase = 0;

+  VirtualMemoryTable[Index].VirtualBase  = 0;

+  VirtualMemoryTable[Index].Length       = 0;

+  VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;

+

+  *VirtualMemoryMap = VirtualMemoryTable;

 }

 

 /**

-  Return the EFI Memory Map of your platform

+  Return the EFI Memory Map provided by extension memory on your platform

 

   This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource

   Descriptor HOBs used by DXE core.