diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:50:59 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:50:59 +0000 |
| commit | 06a8973319faf1aea6260fe2a14dcc40271ad3d1 (patch) | |
| tree | a8fdea9b73d4a12303a7e5687a8160e3df775f20 /ArmPlatformPkg/ArmVExpressPkg | |
| parent | c52e2dca64d90140130444fb647590763b4594ad (diff) | |
| download | edk2-platforms-06a8973319faf1aea6260fe2a14dcc40271ad3d1.tar.xz | |
ArmPlatformPkg/PL34xDmc: Remove DMC base address from the DMC configuration
By removing the DMC Base Address from the structure, we can reuse the same DMC
configuration for two similar DMC controllers.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11960 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/ArmVExpressPkg')
| -rw-r--r-- | ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c index 17d09a605a..644842f6d6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c @@ -29,16 +29,14 @@ // DDR2 timings PL341_DMC_CONFIG DDRTimings = { - .base = ARM_VE_DMC_BASE, - .phy_ctrl_base = 0x0, //There is no DDR2 PHY controller on CTA9 test chip .MaxChip = 1, .IsUserCfg = TRUE, .User0Cfg = 0x7C924924, .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT), .HasQos = TRUE, - .refresh_prd = 0x3D0, - .cas_latency = 0x8, - .write_latency = 0x3, + .RefreshPeriod = 0x3D0, + .CasLatency = 0x8, + .WriteLatency = 0x3, .t_mrd = 0x2, .t_ras = 0xA, .t_rc = 0xE, @@ -153,6 +151,6 @@ ArmPlatformInitializeSystemMemory ( VOID ) { - PL341DmcInit(&DDRTimings); + PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings); PL301AxiInit(ARM_VE_FAXI_BASE); } |