Add ArmPlatformPkg from ARM Ltd. patch.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11291 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 113 insertions, 0 deletions

diff --git a/ArmPlatformPkg/Include/Drivers/PL011Uart.h b/ArmPlatformPkg/Include/Drivers/PL011Uart.h
new file mode 100644
index 0000000000..237dc15c28
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/PL011Uart.h
@@ -0,0 +1,63 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*  
+*  This program and the accompanying materials                          
+*  are licensed and made available under the terms and conditions of the BSD License         
+*  which accompanies this distribution.  The full text of the license may be found at        
+*  http://opensource.org/licenses/bsd-license.php                                            
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+*
+**/
+
+#ifndef __PL011_UART_H__
+#define __PL011_UART_H__
+
+#define SERIAL_PORT_MAX_TIMEOUT            100000000    // 100 seconds
+
+// PL011 Registers
+#define UARTDR          0x000
+#define UARTRSR         0x004
+#define UARTECR         0x004
+#define UARTFR          0x018
+#define UARTILPR        0x020
+#define UARTIBRD        0x024
+#define UARTFBRD        0x028
+#define UARTLCR_H       0x02C
+#define UARTCR          0x030
+#define UARTIFLS        0x034
+#define UARTIMSC        0x038
+#define UARTRIS         0x03C
+#define UARTMIS         0x040
+#define UARTICR         0x044
+#define UARTDMACR       0x048
+
+#define UART_115200_IDIV      13      // Integer Part
+#define UART_115200_FDIV      1       // Fractional Part
+#define UART_38400_IDIV       39
+#define UART_38400_FDIV       5
+#define UART_19200_IDIV       12
+#define UART_19200_FDIV       37
+
+// data status bits
+#define UART_DATA_ERROR_MASK      0x0F00
+
+// status reg bits
+#define UART_STATUS_ERROR_MASK    0x0F
+
+// flag reg bits
+#define UART_TX_EMPTY_FLAG_MASK   0x80
+#define UART_RX_FULL_FLAG_MASK    0x40
+#define UART_TX_FULL_FLAG_MASK    0x20
+#define UART_RX_EMPTY_FLAG_MASK   0x10
+#define UART_BUSY_FLAG_MASK       0x08
+
+// control reg bits
+#define UART_CTSEN_CONTROL_MASK   0x8000
+#define UART_RTSEN_CONTROL_MASK   0x4000
+#define UART_RTS_CONTROL_MASK     0x0800
+#define UART_DTR_CONTROL_MASK     0x0400
+
+#endif
diff --git a/ArmPlatformPkg/Include/Drivers/SP804Timer.h b/ArmPlatformPkg/Include/Drivers/SP804Timer.h
new file mode 100644
index 0000000000..dee337ebf9
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/SP804Timer.h
@@ -0,0 +1,50 @@
+/** @file

+*

+*  Copyright (c) 2011, ARM Limited. All rights reserved.

+*  

+*  This program and the accompanying materials                          

+*  are licensed and made available under the terms and conditions of the BSD License         

+*  which accompanies this distribution.  The full text of the license may be found at        

+*  http://opensource.org/licenses/bsd-license.php                                            

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+*

+**/

+

+

+#ifndef _SP804_TIMER_H__

+#define _SP804_TIMER_H__

+

+// SP804 Timer constants

+#define SP804_TIMER_LOAD_REG          0x00

+#define SP804_TIMER_CURRENT_REG       0x04

+#define SP804_TIMER_CONTROL_REG       0x08

+#define SP804_TIMER_INT_CLR_REG       0x0C

+#define SP804_TIMER_RAW_INT_STS_REG   0x10

+#define SP804_TIMER_MSK_INT_STS_REG   0x14

+#define SP804_TIMER_BG_LOAD_REG       0x18

+

+// Timer control register bit definitions

+#define SP804_TIMER_CTRL_ONESHOT        BIT0

+#define SP804_TIMER_CTRL_32BIT          BIT1

+#define SP804_TIMER_CTRL_PRESCALE_MASK  (BIT3|BIT2)

+#define SP804_PRESCALE_DIV_1            0

+#define SP804_PRESCALE_DIV_16           BIT2

+#define SP804_PRESCALE_DIV_256          BIT3

+#define SP804_TIMER_CTRL_INT_ENABLE     BIT5

+#define SP804_TIMER_CTRL_PERIODIC       BIT6

+#define SP804_TIMER_CTRL_ENABLE         BIT7

+

+// SP810 System Controller constants

+#define SP810_SYS_CTRL_REG              0x00

+#define SP810_SYS_CTRL_TIMER0_TIMCLK    BIT15 // 0=REFCLK, 1=TIMCLK

+#define SP810_SYS_CTRL_TIMER0_EN        BIT16

+#define SP810_SYS_CTRL_TIMER1_TIMCLK    BIT17 // 0=REFCLK, 1=TIMCLK

+#define SP810_SYS_CTRL_TIMER1_EN        BIT18

+#define SP810_SYS_CTRL_TIMER2_TIMCLK    BIT19 // 0=REFCLK, 1=TIMCLK

+#define SP810_SYS_CTRL_TIMER2_EN        BIT20

+#define SP810_SYS_CTRL_TIMER3_TIMCLK    BIT21 // 0=REFCLK, 1=TIMCLK

+#define SP810_SYS_CTRL_TIMER3_EN        BIT22

+

+#endif