ArmPkg: Move ARM Platform drivers from ArmPkg/Drivers/ to ArmPlatformPkg/Drivers/

The idea is to keep ArmPkg responsible for the ARM architectural modules and ArmPlatformPkg
the ARM development platform packages (with their respective drivers).


ArmPlatformPkg: Reduce driver dependency on ArmPlatform.h

- Move some driver definitions from C-Macro to PCD values
- Unify PCD driver namespace




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11956 6f19259b-4bc3-4df7-8a09-765794883524

8 files changed, 578 insertions, 85 deletions

diff --git a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
index 8c26d66053..4c559c0c95 100644
--- a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
+++ b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h
@@ -16,26 +16,23 @@
 #ifndef __PL031_REAL_TIME_CLOCK_H__

 #define __PL031_REAL_TIME_CLOCK_H__

 

-#include <Base.h>

-#include <ArmPlatform.h>

-

 // PL031 Registers

-#define PL031_RTC_DR_DATA_REGISTER                      (PL031_RTC_BASE + 0x000)

-#define PL031_RTC_MR_MATCH_REGISTER                     (PL031_RTC_BASE + 0x004)

-#define PL031_RTC_LR_LOAD_REGISTER                      (PL031_RTC_BASE + 0x008)

-#define PL031_RTC_CR_CONTROL_REGISTER                   (PL031_RTC_BASE + 0x00C)

-#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER      (PL031_RTC_BASE + 0x010)

-#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER           (PL031_RTC_BASE + 0x014)

-#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER        (PL031_RTC_BASE + 0x018)

-#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER                (PL031_RTC_BASE + 0x01C)

-#define PL031_RTC_PERIPH_ID0                            (PL031_RTC_BASE + 0xFE0)

-#define PL031_RTC_PERIPH_ID1                            (PL031_RTC_BASE + 0xFE4)

-#define PL031_RTC_PERIPH_ID2                            (PL031_RTC_BASE + 0xFE8)

-#define PL031_RTC_PERIPH_ID3                            (PL031_RTC_BASE + 0xFEC)

-#define PL031_RTC_PCELL_ID0                             (PL031_RTC_BASE + 0xFF0)

-#define PL031_RTC_PCELL_ID1                             (PL031_RTC_BASE + 0xFF4)

-#define PL031_RTC_PCELL_ID2                             (PL031_RTC_BASE + 0xFF8)

-#define PL031_RTC_PCELL_ID3                             (PL031_RTC_BASE + 0xFFC)

+#define PL031_RTC_DR_DATA_REGISTER                      ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x000)

+#define PL031_RTC_MR_MATCH_REGISTER                     ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x004)

+#define PL031_RTC_LR_LOAD_REGISTER                      ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x008)

+#define PL031_RTC_CR_CONTROL_REGISTER                   ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x00C)

+#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER      ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x010)

+#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER           ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x014)

+#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER        ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x018)

+#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER                ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x01C)

+#define PL031_RTC_PERIPH_ID0                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE0)

+#define PL031_RTC_PERIPH_ID1                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE4)

+#define PL031_RTC_PERIPH_ID2                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE8)

+#define PL031_RTC_PERIPH_ID3                            ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFEC)

+#define PL031_RTC_PCELL_ID0                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF0)

+#define PL031_RTC_PCELL_ID1                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF4)

+#define PL031_RTC_PCELL_ID2                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF8)

+#define PL031_RTC_PCELL_ID3                             ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFFC)

 

 // PL031 Values

 #define PL031_RTC_ENABLED                               0x00000001

diff --git a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
index 4daabff768..739caaf2a1 100644
--- a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
+++ b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h
@@ -16,31 +16,29 @@
 #ifndef __PL061_GPIO_H__

 #define __PL061_GPIO_H__

 

-#include <Base.h>

 #include <Protocol/EmbeddedGpio.h>

-#include <ArmPlatform.h>

 

 // SP805 Watchdog Registers

-#define PL061_GPIO_DATA_REG             (PL061_GPIO_BASE + 0x000)

-#define PL061_GPIO_DIR_REG              (PL061_GPIO_BASE + 0x400)

-#define PL061_GPIO_IS_REG               (PL061_GPIO_BASE + 0x404)

-#define PL061_GPIO_IBE_REG              (PL061_GPIO_BASE + 0x408)

-#define PL061_GPIO_IEV_REG              (PL061_GPIO_BASE + 0x40C)

-#define PL061_GPIO_IE_REG               (PL061_GPIO_BASE + 0x410)

-#define PL061_GPIO_RIS_REG              (PL061_GPIO_BASE + 0x414)

-#define PL061_GPIO_MIS_REG              (PL061_GPIO_BASE + 0x410)

-#define PL061_GPIO_IC_REG               (PL061_GPIO_BASE + 0x41C)

-#define PL061_GPIO_AFSEL_REG            (PL061_GPIO_BASE + 0x420)

-

-#define PL061_GPIO_PERIPH_ID0           (PL061_GPIO_BASE + 0xFE0)

-#define PL061_GPIO_PERIPH_ID1           (PL061_GPIO_BASE + 0xFE4)

-#define PL061_GPIO_PERIPH_ID2           (PL061_GPIO_BASE + 0xFE8)

-#define PL061_GPIO_PERIPH_ID3           (PL061_GPIO_BASE + 0xFEC)

-

-#define PL061_GPIO_PCELL_ID0            (PL061_GPIO_BASE + 0xFF0)

-#define PL061_GPIO_PCELL_ID1            (PL061_GPIO_BASE + 0xFF4)

-#define PL061_GPIO_PCELL_ID2            (PL061_GPIO_BASE + 0xFF8)

-#define PL061_GPIO_PCELL_ID3            (PL061_GPIO_BASE + 0xFFC)

+#define PL061_GPIO_DATA_REG             ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)

+#define PL061_GPIO_DIR_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)

+#define PL061_GPIO_IS_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)

+#define PL061_GPIO_IBE_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x408)

+#define PL061_GPIO_IEV_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x40C)

+#define PL061_GPIO_IE_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)

+#define PL061_GPIO_RIS_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x414)

+#define PL061_GPIO_MIS_REG              ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)

+#define PL061_GPIO_IC_REG               ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x41C)

+#define PL061_GPIO_AFSEL_REG            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x420)

+

+#define PL061_GPIO_PERIPH_ID0           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE0)

+#define PL061_GPIO_PERIPH_ID1           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE4)

+#define PL061_GPIO_PERIPH_ID2           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE8)

+#define PL061_GPIO_PERIPH_ID3           ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFEC)

+

+#define PL061_GPIO_PCELL_ID0            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF0)

+#define PL061_GPIO_PCELL_ID1            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF4)

+#define PL061_GPIO_PCELL_ID2            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF8)

+#define PL061_GPIO_PCELL_ID3            ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFFC)

 

 

 // GPIO pins are numbered 0..7

diff --git a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h b/ArmPlatformPkg/Include/Drivers/PL111Lcd.h
index 80d563976d..d68acd83b3 100644
--- a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h
+++ b/ArmPlatformPkg/Include/Drivers/PL111Lcd.h
@@ -14,8 +14,6 @@
 #ifndef _PL111LCD_H__
 #define _PL111LCD_H__
 
-#include <ArmPlatform.h>
-
 /**********************************************************************
  *
  *  This header file contains all the bits of the PL111 that are
@@ -24,30 +22,30 @@
  **********************************************************************/
 
 // Controller Register Offsets
-#define PL111_REG_LCD_TIMING_0            (PL111_CLCD_BASE + 0x000)
-#define PL111_REG_LCD_TIMING_1            (PL111_CLCD_BASE + 0x004)
-#define PL111_REG_LCD_TIMING_2            (PL111_CLCD_BASE + 0x008)
-#define PL111_REG_LCD_TIMING_3            (PL111_CLCD_BASE + 0x00C)
-#define PL111_REG_LCD_UP_BASE             (PL111_CLCD_BASE + 0x010)
-#define PL111_REG_LCD_LP_BASE             (PL111_CLCD_BASE + 0x014)
-#define PL111_REG_LCD_CONTROL             (PL111_CLCD_BASE + 0x018)
-#define PL111_REG_LCD_IMSC                (PL111_CLCD_BASE + 0x01C)
-#define PL111_REG_LCD_RIS                 (PL111_CLCD_BASE + 0x020)
-#define PL111_REG_LCD_MIS                 (PL111_CLCD_BASE + 0x024)
-#define PL111_REG_LCD_ICR                 (PL111_CLCD_BASE + 0x028)
-#define PL111_REG_LCD_UP_CURR             (PL111_CLCD_BASE + 0x02C)
-#define PL111_REG_LCD_LP_CURR             (PL111_CLCD_BASE + 0x030)
-#define PL111_REG_LCD_PALETTE             (PL111_CLCD_BASE + 0x200)
+#define PL111_REG_LCD_TIMING_0            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
+#define PL111_REG_LCD_TIMING_1            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
+#define PL111_REG_LCD_TIMING_2            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
+#define PL111_REG_LCD_TIMING_3            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
+#define PL111_REG_LCD_UP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
+#define PL111_REG_LCD_LP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
+#define PL111_REG_LCD_CONTROL             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
+#define PL111_REG_LCD_IMSC                ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
+#define PL111_REG_LCD_RIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
+#define PL111_REG_LCD_MIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
+#define PL111_REG_LCD_ICR                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
+#define PL111_REG_LCD_UP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
+#define PL111_REG_LCD_LP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
+#define PL111_REG_LCD_PALETTE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
 
 // Identification Register Offsets
-#define PL111_REG_CLCD_PERIPH_ID_0        (PL111_CLCD_BASE + 0xFE0)
-#define PL111_REG_CLCD_PERIPH_ID_1        (PL111_CLCD_BASE + 0xFE4)
-#define PL111_REG_CLCD_PERIPH_ID_2        (PL111_CLCD_BASE + 0xFE8)
-#define PL111_REG_CLCD_PERIPH_ID_3        (PL111_CLCD_BASE + 0xFEC)
-#define PL111_REG_CLCD_P_CELL_ID_0        (PL111_CLCD_BASE + 0xFF0)
-#define PL111_REG_CLCD_P_CELL_ID_1        (PL111_CLCD_BASE + 0xFF4)
-#define PL111_REG_CLCD_P_CELL_ID_2        (PL111_CLCD_BASE + 0xFF8)
-#define PL111_REG_CLCD_P_CELL_ID_3        (PL111_CLCD_BASE + 0xFFC)
+#define PL111_REG_CLCD_PERIPH_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
+#define PL111_REG_CLCD_PERIPH_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
+#define PL111_REG_CLCD_PERIPH_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
+#define PL111_REG_CLCD_PERIPH_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
+#define PL111_REG_CLCD_P_CELL_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
+#define PL111_REG_CLCD_P_CELL_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
+#define PL111_REG_CLCD_P_CELL_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
+#define PL111_REG_CLCD_P_CELL_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
 
 /**********************************************************************/
 
diff --git a/ArmPlatformPkg/Include/Drivers/PL301Axi.h b/ArmPlatformPkg/Include/Drivers/PL301Axi.h
new file mode 100644
index 0000000000..1bf936ff78
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/PL301Axi.h
@@ -0,0 +1,21 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PL301AXI_H_
+#define PL301AXI_H_
+
+VOID PL301AxiInit(UINTN FAxiBase);
+
+
+#endif /* PL301AXI_H_ */
diff --git a/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h b/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h
new file mode 100644
index 0000000000..a610998062
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h
@@ -0,0 +1,79 @@
+/** @file

+*

+*  Copyright (c) 2011, ARM Limited. All rights reserved.

+*

+*  This program and the accompanying materials

+*  are licensed and made available under the terms and conditions of the BSD License

+*  which accompanies this distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+*

+**/

+

+#ifndef L2CACHELIB_H_

+#define L2CACHELIB_H_

+

+#define L2X0_CACHEID            0x000

+#define L2X0_CTRL               0x100

+#define L2X0_AUXCTRL            0x104

+#define L230_TAG_LATENCY        0x108

+#define L230_DATA_LATENCY       0x10C

+#define L2X0_INTCLEAR           0x220

+#define L2X0_CACHE_SYNC         0x730

+#define L2X0_INVWAY             0x77C

+#define L2X0_CLEAN_WAY          0x7BC

+#define L2X0_PFCTRL             0xF60

+#define L2X0_PWRCTRL            0xF80

+

+#define L2X0_CACHEID_IMPLEMENTER_ARM        0x41

+#define L2X0_CACHEID_PARTNUM_PL310          0x03

+

+#define L2X0_CTRL_ENABLED                   0x1

+#define L2X0_CTRL_DISABLED                  0x0

+

+#define L2X0_AUXCTRL_EXCLUSIVE              (1 << 12)

+#define L2X0_AUXCTRL_ASSOCIATIVITY          (1 << 16)

+#define L2X0_AUXCTRL_WAYSIZE_MASK           (3 << 17)

+#define L2X0_AUXCTRL_WAYSIZE_16KB           (1 << 17)

+#define L2X0_AUXCTRL_WAYSIZE_32KB           (2 << 17)

+#define L2X0_AUXCTRL_WAYSIZE_64KB           (3 << 17)

+#define L2X0_AUXCTRL_WAYSIZE_128KB          (4 << 17)

+#define L2X0_AUXCTRL_WAYSIZE_256KB          (5 << 17)

+#define L2X0_AUXCTRL_WAYSIZE_512KB          (6 << 17)

+#define L2X0_AUXCTRL_EM                     (1 << 20)

+#define L2X0_AUXCTRL_SHARED_OVERRIDE        (1 << 22)

+#define L2x0_AUXCTRL_AW_AWCACHE             (0 << 23)

+#define L2x0_AUXCTRL_AW_NOALLOC             (1 << 23)

+#define L2x0_AUXCTRL_AW_OVERRIDE            (2 << 23)

+#define L2X0_AUXCTRL_SBO                    (1 << 25)

+#define L2X0_AUXCTRL_NSAC                   (1 << 27)

+#define L2x0_AUXCTRL_DPREFETCH              (1 << 28)

+#define L2x0_AUXCTRL_IPREFETCH              (1 << 29)

+#define L2x0_AUXCTRL_EARLY_BRESP            (1 << 30)

+

+#define L2x0_LATENCY_1_CYCLE                 0

+#define L2x0_LATENCY_2_CYCLES                1

+#define L2x0_LATENCY_3_CYCLES                2

+#define L2x0_LATENCY_4_CYCLES                3

+#define L2x0_LATENCY_5_CYCLES                4

+#define L2x0_LATENCY_6_CYCLES                5

+#define L2x0_LATENCY_7_CYCLES                6

+#define L2x0_LATENCY_8_CYCLES                7

+

+#define PL310_LATENCIES(Write,Read,Setup)      (((Write) << 8) | ((Read) << 4) | (Setup))

+#define PL310_TAG_LATENCIES(Write,Read,Setup)  PL310_LATENCIES(Write,Read,Setup)

+#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)

+

+VOID

+L2x0CacheInit (

+  IN  UINTN   L2x0Base,

+  IN  UINT32  L2x0TagLatencies,

+  IN  UINT32  L2x0DataLatencies,

+  IN  UINT32  L2x0AuxValue,

+  IN  UINT32  L2x0AuxMask,

+  IN  BOOLEAN CacheEnabled

+  );

+

+#endif /* L2CACHELIB_H_ */

diff --git a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h
new file mode 100644
index 0000000000..461ec16cc2
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h
@@ -0,0 +1,346 @@
+/** @file
+*
+*  Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _PL341DMC_H_
+#define _PL341DMC_H_
+
+
+typedef struct  {
+    UINTN	base;           // base address for the controller
+    UINTN	phy_ctrl_base;	// DDR2 Phy control base
+    UINTN	HasQos;        // has QoS registers
+    UINTN	MaxChip;       // number of memory chips accessible
+    BOOLEAN  IsUserCfg;
+    UINT32  User0Cfg;
+    UINT32  User2Cfg;
+    UINT32	refresh_prd;
+    UINT32	cas_latency;
+    UINT32	write_latency;
+    UINT32	t_mrd;
+    UINT32	t_ras;
+    UINT32	t_rc;
+    UINT32	t_rcd;
+    UINT32	t_rfc;
+    UINT32	t_rp;
+    UINT32	t_rrd;
+    UINT32	t_wr;
+    UINT32	t_wtr;
+    UINT32	t_xp;
+    UINT32	t_xsr;
+    UINT32	t_esr;
+    UINT32	MemoryCfg;
+    UINT32	MemoryCfg2;
+    UINT32	MemoryCfg3;
+    UINT32	ChipCfg0;
+    UINT32	ChipCfg1;
+    UINT32	ChipCfg2;
+    UINT32	ChipCfg3;
+    UINT32	t_faw;
+    UINT32	t_data_en;
+    UINT32	t_wdata_en;
+    UINT32  ModeReg;
+    UINT32  ExtModeReg;
+} PL341_DMC_CONFIG;
+
+/* Memory config bit fields */
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9      0x1
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10     0x2
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11     0x3
+#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12     0x4
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11        (0x0 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12        (0x1 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13        (0x2 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14        (0x3 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15        (0x4 << 3)
+#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16        (0x5 << 3)
+#define DMC_MEMORY_CONFIG_BURST_2               (0x1 << 15)
+#define DMC_MEMORY_CONFIG_BURST_4               (0x2 << 15)
+#define DMC_MEMORY_CONFIG_BURST_8               (0x3 << 15)
+#define DMC_MEMORY_CONFIG_BURST_16              (0x4 << 15)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1    (0x0 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2    (0x1 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3    (0x2 << 21)
+#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4    (0x3 << 21)
+
+#define DMC_MEMORY_CFG2_CLK_ASYNC    (0x0 << 0)
+#define DMC_MEMORY_CFG2_CLK_SYNC    (0x1 << 0)
+#define DMC_MEMORY_CFG2_DQM_INIT    (0x1 << 2)
+#define DMC_MEMORY_CFG2_CKE_INIT    (0x1 << 3)
+#define DMC_MEMORY_CFG2_BANK_BITS_2    (0x0 << 4)
+#define DMC_MEMORY_CFG2_BANK_BITS_3    (0x3 << 4)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_16    (0x0 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_32    (0x1 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_64    (0x2 << 6)
+#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED  (0x3 << 6)
+
+//
+// DMC Configuration Register Map
+//
+#define DMC_STATUS_REG              0x00
+#define DMC_COMMAND_REG             0x04
+#define DMC_DIRECT_CMD_REG          0x08
+#define DMC_MEMORY_CONFIG_REG       0x0C
+#define DMC_REFRESH_PRD_REG         0x10
+#define DMC_CAS_LATENCY_REG         0x14
+#define DMC_WRITE_LATENCY_REG       0x18
+#define DMC_T_MRD_REG               0x1C
+#define DMC_T_RAS_REG               0x20
+#define DMC_T_RC_REG                0x24
+#define DMC_T_RCD_REG               0x28
+#define DMC_T_RFC_REG               0x2C
+#define DMC_T_RP_REG                0x30
+#define DMC_T_RRD_REG               0x34
+#define DMC_T_WR_REG                0x38
+#define DMC_T_WTR_REG               0x3C
+#define DMC_T_XP_REG                0x40
+#define DMC_T_XSR_REG               0x44
+#define DMC_T_ESR_REG               0x48
+#define DMC_MEMORY_CFG2_REG         0x4C
+#define DMC_MEMORY_CFG3_REG         0x50
+#define DMC_T_FAW_REG               0x54
+#define DMC_T_RDATA_EN              0x5C	/* DFI read data enable register */
+#define DMC_T_WRLAT_DIFF            0x60        /* DFI write data enable register */
+
+// Returns the state of the memory controller:
+#define DMC_STATUS_CONFIG       0x0
+#define DMC_STATUS_READY        0x1
+#define DMC_STATUS_PAUSED       0x2
+#define DMC_STATUS_LOWPOWER     0x3
+
+// Changes the state of the memory controller:
+#define DMC_COMMAND_GO              0x0
+#define DMC_COMMAND_SLEEP           0x1
+#define DMC_COMMAND_WAKEUP          0x2
+#define DMC_COMMAND_PAUSE           0x3
+#define DMC_COMMAND_CONFIGURE       0x4
+#define DMC_COMMAND_ACTIVEPAUSE     0x7
+
+// Determines the command required
+#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL      0x0
+#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH       (0x1 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_MODEREG           (0x2 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG        (0x2 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_NOP               (0x3 << 18)
+#define DMC_DIRECT_CMD_MEMCMD_DPD               (0x1 << 22)
+#define DMC_DIRECT_CMD_BANKADDR(n)              ((n & 0x3) << 16)
+#define DMC_DIRECT_CMD_CHIP_ADDR(n)             ((n & 0x3) << 20)
+
+
+//
+// AXI ID configuration register map
+//
+#define DMC_ID_0_CFG_REG            0x100
+#define DMC_ID_1_CFG_REG            0x104
+#define DMC_ID_2_CFG_REG            0x108
+#define DMC_ID_3_CFG_REG            0x10C
+#define DMC_ID_4_CFG_REG            0x110
+#define DMC_ID_5_CFG_REG            0x114
+#define DMC_ID_6_CFG_REG            0x118
+#define DMC_ID_7_CFG_REG            0x11C
+#define DMC_ID_8_CFG_REG            0x120
+#define DMC_ID_9_CFG_REG            0x124
+#define DMC_ID_10_CFG_REG           0x128
+#define DMC_ID_11_CFG_REG           0x12C
+#define DMC_ID_12_CFG_REG           0x130
+#define DMC_ID_13_CFG_REG           0x134
+#define DMC_ID_14_CFG_REG           0x138
+#define DMC_ID_15_CFG_REG           0x13C
+
+// Set the QoS
+#define DMC_ID_CFG_QOS_DISABLE      0
+#define DMC_ID_CFG_QOS_ENABLE       1
+#define DMC_ID_CFG_QOS_MIN          2
+
+
+//
+// Chip configuration register map
+//
+#define DMC_CHIP_0_CFG_REG          0x200
+#define DMC_CHIP_1_CFG_REG          0x204
+#define DMC_CHIP_2_CFG_REG          0x208
+#define DMC_CHIP_3_CFG_REG          0x20C
+
+//
+// User Defined Pins
+//
+#define DMC_USER_STATUS_REG         0x300
+#define DMC_USER_0_CFG_REG          0x304
+#define DMC_USER_1_CFG_REG          0x308
+#define DMC_FEATURE_CRTL_REG        0x30C
+#define DMC_USER_2_CFG_REG          0x310
+
+
+//
+// PHY Register Settings
+//
+#define PHY_PTM_DFI_CLK_RANGE					0xE00		// DDR2 PHY PTM register offset
+#define PHY_PTM_IOTERM							0xE04
+#define PHY_PTM_PLL_EN          				0xe0c
+#define PHY_PTM_PLL_RANGE       				0xe18
+#define PHY_PTM_FEEBACK_DIV     				0xe1c
+#define PHY_PTM_RCLK_DIV        				0xe20
+#define PHY_PTM_LOCK_STATUS     				0xe28
+#define PHY_PTM_INIT_DONE	     				0xe34
+#define PHY_PTM_ADDCOM_IOSTR_OFF				0xec8
+#define PHY_PTM_SQU_TRAINING    				0xee8
+#define PHY_PTM_SQU_STAT        				0xeec
+
+// ==============================================================================
+// PIPD 40G DDR2/DDR3 PHY Register definitions
+//
+// Offsets from APB Base Address
+// ==============================================================================
+#define PHY_BYTE0_OFFSET					0x000
+#define PHY_BYTE1_OFFSET					0x200
+#define PHY_BYTE2_OFFSET					0x400
+#define PHY_BYTE3_OFFSET					0x600
+
+#define PHY_BYTE0_COARSE_SQADJ_INIT			0x064	;// Coarse squelch adjust
+#define PHY_BYTE1_COARSE_SQADJ_INIT			0x264	;// Coarse squelch adjust
+#define PHY_BYTE2_COARSE_SQADJ_INIT			0x464	;// Coarse squelch adjust
+#define PHY_BYTE3_COARSE_SQADJ_INIT			0x664	;// Coarse squelch adjust
+
+#define PHY_BYTE0_IOSTR_OFFSET				0x004
+#define PHY_BYTE1_IOSTR_OFFSET				0x204
+#define PHY_BYTE2_IOSTR_OFFSET				0x404
+#define PHY_BYTE3_IOSTR_OFFSET				0x604
+
+
+;//--------------------------------------------------------------------------
+
+// DFI Clock ranges:
+
+#define PHY_PTM_DFI_CLK_RANGE_200MHz   		0x0
+#define PHY_PTM_DFI_CLK_RANGE_201_267MHz	0x1
+#define PHY_PTM_DFI_CLK_RANGE_268_333MHz	0x2
+#define PHY_PTM_DFI_CLK_RANGE_334_400MHz	0x3
+#define PHY_PTM_DFI_CLK_RANGE_401_533MHz	0x4
+#define PHY_PTM_DFI_CLK_RANGE_534_667MHz	0x5
+#define PHY_PTM_DFI_CLK_RANGE_668_800MHz	0x6
+
+
+
+#define  PHY_PTM_DFI_CLK_RANGE_VAL			PHY_PTM_DFI_CLK_RANGE_334_400MHz
+
+//--------------------------------------------------------------------------
+
+
+// PLL Range
+
+#define PHY_PTM_PLL_RANGE_200_400MHz		0x0	// b0 = frequency >= 200 MHz and < 400 MHz
+#define PHY_PTM_PLL_RANGE_400_800MHz		0x1	// b1 = frequency >= 400 MHz.
+#define PHY_PTM_FEEBACK_DIV_200_400MHz		0x0	// b0 = frequency >= 200 MHz and < 400 MHz
+#define PHY_PTM_FEEBACK_DIV_400_800MHz		0x1	// b1 = frequency >= 400 MHz.
+#define PHY_PTM_REFCLK_DIV_200_400MHz		0x0
+#define PHY_PTM_REFCLK_DIV_400_800MHz		0x1
+
+
+// PHY Reset in SCC
+
+#define SCC_PHY_RST_REG_OFF	        		0xA0
+#define SCC_REMAP_REG_OFF   	       		0x00
+#define SCC_PHY_RST0_MASK					1		// Active LOW PHY0 reset
+#define SCC_PHY_RST0_SHFT					0		// Active LOW PHY0 reset
+#define SCC_PHY_RST1_MASK					0x100	// Active LOW PHY1 reset
+#define SCC_PHY_RST1_SHFT					8		// Active LOW PHY1 reset
+
+#define TC_UIOLHNC_MASK                         0x000003C0
+#define TC_UIOLHNC_SHIFT                        0x6
+#define TC_UIOLHPC_MASK                         0x0000003F
+#define TC_UIOLHPC_SHIFT                        0x2
+#define TC_UIOHOCT_MASK                         0x2
+#define TC_UIOHOCT_SHIFT                        0x1
+#define TC_UIOHSTOP_SHIFT                       0x0
+#define TC_UIOLHXC_VALUE                        0x4
+
+#define PHY_PTM_SQU_TRAINING_ENABLE				0x1
+#define PHY_PTM_SQU_TRAINING_DISABLE				0x0
+
+
+//--------------------------------------
+// JEDEC DDR2 Device Register definitions and settings
+//--------------------------------------
+#define DDR_MODESET_SHFT						14
+#define DDR_MODESET_MR							0x0		;// Mode register
+#define DDR_MODESET_EMR							0x1		;// Extended Mode register
+#define DDR_MODESET_EMR2						0x2
+#define DDR_MODESET_EMR3						0x3
+
+//
+// Extended Mode Register settings
+//
+#define DDR_EMR_OCD_MASK                        0x0000380
+#define DDR_EMR_OCD_SHIFT                       0x7
+#define DDR_EMR_RTT_MASK                        0x00000044                  // DDR2 Device RTT (ODT) settings
+#define DDR_EMR_RTT_SHIFT                       0x2
+#define DDR_EMR_ODS_MASK                        0x00000002                  // DDR2 Output Drive Strength
+#define DDR_EMR_ODS_SHIFT                       0x0001
+
+// Termination Values:
+#define DDR_EMR_RTT_50R                         0x00000044                  // DDR2 50 Ohm termination
+#define DDR_EMR_RTT_75R                         0x00000004                  // DDR2 75 Ohm termination
+#define DDR_EMR_RTT_150                         0x00000040                  // DDR2 150 Ohm termination
+
+// Output Drive Strength Values:
+#define DDR_EMR_ODS_FULL                        0x0                         // DDR2 Full Drive Strength
+#define DDR_EMR_ODS_HALF                        0x1                         // DDR2 Half Drive Strength
+
+// OCD values
+#define DDR_EMR_OCD_DEFAULT                     0x7
+#define DDR_EMR_OCD_NS                          0x0
+
+#define DDR_EMR_ODS_VAL                         DDR_EMR_ODS_FULL
+
+#define DDR_SDRAM_START_ADDR					0x10000000
+
+
+// ----------------------------------------
+// PHY IOTERM values
+// ----------------------------------------
+#define PHY_PTM_IOTERM_OFF					0x0
+#define PHY_PTM_IOTERM_150R					0x1
+#define PHY_PTM_IOTERM_75R					0x2
+#define PHY_PTM_IOTERM_50R					0x3
+
+#define PHY_BYTE_IOSTR_60OHM				0x0
+#define PHY_BYTE_IOSTR_40OHM				0x1
+#define PHY_BYTE_IOSTR_30OHM				0x2
+#define PHY_BYTE_IOSTR_30AOHM				0x3
+
+#define DDR2_MR_BURST_LENGTH_4     (2)
+#define DDR2_MR_BURST_LENGTH_8     (3)
+#define DDR2_MR_DLL_RESET          (1 << 8)
+#define DDR2_MR_CAS_LATENCY_4      (4 << 4)
+#define DDR2_MR_CAS_LATENCY_5      (5 << 4)
+#define DDR2_MR_CAS_LATENCY_6      (6 << 4)
+#define DDR2_MR_WR_CYCLES_2        (1 << 9)
+#define DDR2_MR_WR_CYCLES_3        (2 << 9)
+#define DDR2_MR_WR_CYCLES_4        (3 << 9)
+#define DDR2_MR_WR_CYCLES_5        (4 << 9)
+#define DDR2_MR_WR_CYCLES_6        (5 << 9)
+
+
+VOID PL341DmcInit (
+  IN PL341_DMC_CONFIG *config
+  );
+
+VOID PL341DmcPhyInit (
+  IN UINTN   DmcPhyBase
+  );
+
+VOID PL341DmcTrainPHY (
+  IN UINTN   DmcPhyBase
+  );
+
+#endif /* _PL341DMC_H_ */
diff --git a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
new file mode 100644
index 0000000000..0da47f9982
--- /dev/null
+++ b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
@@ -0,0 +1,57 @@
+/** @file

+*

+*  Copyright (c) 2011, ARM Limited. All rights reserved.

+*

+*  This program and the accompanying materials

+*  are licensed and made available under the terms and conditions of the BSD License

+*  which accompanies this distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+*

+**/

+

+#ifndef PL354SMC_H_

+#define PL354SMC_H_

+

+#define PL354_SMC_DIRECT_CMD_OFFSET  0x10

+#define PL354_SMC_SET_CYCLES_OFFSET  0x14

+#define PL354_SMC_SET_OPMODE_OFFSET  0x18

+

+#define PL354_SMC_DIRECT_CMD_ADDR(addr)             ((addr) & 0xFFFFF)

+#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE           (1 << 20)

+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE   (3 << 21)

+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE        (2 << 21)

+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE          (1 << 21)

+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI    (0 << 21)

+#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip)   (((interf) << 25) | ((chip) << 23))

+

+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8                (0 << 0)

+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16               (1 << 0)

+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32               (2 << 0)

+#define PL354_SMC_SET_OPMODE_SET_RD_SYNC                (1 << 2)

+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1      (0 << 3)

+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4      (1 << 3)

+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8      (2 << 3)

+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16     (3 << 3)

+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32     (4 << 3)

+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT   (5 << 3)

+#define PL354_SMC_SET_OPMODE_SET_WR_SYNC                (1 << 6)

+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1      (0 << 7)

+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4      (1 << 7)

+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8      (2 << 7)

+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16     (3 << 7)

+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32     (4 << 7)

+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT   (5 << 7)

+#define PL354_SMC_SET_OPMODE_SET_BAA                    (1 << 10)

+#define PL354_SMC_SET_OPMODE_SET_ADV                    (1 << 11)

+#define PL354_SMC_SET_OPMODE_SET_BLS                    (1 << 12)

+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY        (0 << 13)

+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32         (1 << 13)

+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64         (2 << 13)

+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128        (3 << 13)

+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256        (4 << 13)

+

+

+#endif

diff --git a/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h b/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h
index 10600a1553..60c02be139 100644
--- a/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h
+++ b/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h
@@ -16,27 +16,24 @@
 #ifndef __SP805_WATCHDOG_H__

 #define __SP805_WATCHDOG_H__

 

-#include <Base.h>

-#include <ArmPlatform.h>

-

 // SP805 Watchdog Registers

-#define SP805_WDOG_LOAD_REG             (SP805_WDOG_BASE + 0x000)

-#define SP805_WDOG_CURRENT_REG          (SP805_WDOG_BASE + 0x004)

-#define SP805_WDOG_CONTROL_REG          (SP805_WDOG_BASE + 0x008)

-#define SP805_WDOG_INT_CLR_REG          (SP805_WDOG_BASE + 0x00C)

-#define SP805_WDOG_RAW_INT_STS_REG      (SP805_WDOG_BASE + 0x010)

-#define SP805_WDOG_MSK_INT_STS_REG      (SP805_WDOG_BASE + 0x014)

-#define SP805_WDOG_LOCK_REG             (SP805_WDOG_BASE + 0xC00)

-

-#define SP805_WDOG_PERIPH_ID0           (SP805_WDOG_BASE + 0xFE0)

-#define SP805_WDOG_PERIPH_ID1           (SP805_WDOG_BASE + 0xFE4)

-#define SP805_WDOG_PERIPH_ID2           (SP805_WDOG_BASE + 0xFE8)

-#define SP805_WDOG_PERIPH_ID3           (SP805_WDOG_BASE + 0xFEC)

-

-#define SP805_WDOG_PCELL_ID0            (SP805_WDOG_BASE + 0xFF0)

-#define SP805_WDOG_PCELL_ID1            (SP805_WDOG_BASE + 0xFF4)

-#define SP805_WDOG_PCELL_ID2            (SP805_WDOG_BASE + 0xFF8)

-#define SP805_WDOG_PCELL_ID3            (SP805_WDOG_BASE + 0xFFC)

+#define SP805_WDOG_LOAD_REG             ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)

+#define SP805_WDOG_CURRENT_REG          ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)

+#define SP805_WDOG_CONTROL_REG          ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)

+#define SP805_WDOG_INT_CLR_REG          ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)

+#define SP805_WDOG_RAW_INT_STS_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)

+#define SP805_WDOG_MSK_INT_STS_REG      ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)

+#define SP805_WDOG_LOCK_REG             ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)

+

+#define SP805_WDOG_PERIPH_ID0           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)

+#define SP805_WDOG_PERIPH_ID1           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)

+#define SP805_WDOG_PERIPH_ID2           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)

+#define SP805_WDOG_PERIPH_ID3           ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)

+

+#define SP805_WDOG_PCELL_ID0            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)

+#define SP805_WDOG_PCELL_ID1            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)

+#define SP805_WDOG_PCELL_ID2            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)

+#define SP805_WDOG_PCELL_ID3            ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)

 

 // Timer control register bit definitions

 #define SP805_WDOG_CTRL_INTEN           BIT0