diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:50:59 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:50:59 +0000 |
| commit | 06a8973319faf1aea6260fe2a14dcc40271ad3d1 (patch) | |
| tree | a8fdea9b73d4a12303a7e5687a8160e3df775f20 /ArmPlatformPkg/Include | |
| parent | c52e2dca64d90140130444fb647590763b4594ad (diff) | |
| download | edk2-platforms-06a8973319faf1aea6260fe2a14dcc40271ad3d1.tar.xz | |
ArmPlatformPkg/PL34xDmc: Remove DMC base address from the DMC configuration
By removing the DMC Base Address from the structure, we can reuse the same DMC
configuration for two similar DMC controllers.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11960 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/Include')
| -rw-r--r-- | ArmPlatformPkg/Include/Drivers/PL341Dmc.h | 24 |
1 files changed, 7 insertions, 17 deletions
diff --git a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h index 461ec16cc2..0227ced454 100644 --- a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h +++ b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h @@ -17,16 +17,14 @@ typedef struct { - UINTN base; // base address for the controller - UINTN phy_ctrl_base; // DDR2 Phy control base UINTN HasQos; // has QoS registers UINTN MaxChip; // number of memory chips accessible BOOLEAN IsUserCfg; UINT32 User0Cfg; UINT32 User2Cfg; - UINT32 refresh_prd; - UINT32 cas_latency; - UINT32 write_latency; + UINT32 RefreshPeriod; + UINT32 CasLatency; + UINT32 WriteLatency; UINT32 t_mrd; UINT32 t_ras; UINT32 t_rc; @@ -245,16 +243,6 @@ typedef struct { #define PHY_PTM_REFCLK_DIV_200_400MHz 0x0 #define PHY_PTM_REFCLK_DIV_400_800MHz 0x1 - -// PHY Reset in SCC - -#define SCC_PHY_RST_REG_OFF 0xA0 -#define SCC_REMAP_REG_OFF 0x00 -#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset -#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset -#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset -#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset - #define TC_UIOLHNC_MASK 0x000003C0 #define TC_UIOLHNC_SHIFT 0x6 #define TC_UIOLHPC_MASK 0x0000003F @@ -331,8 +319,10 @@ typedef struct { #define DDR2_MR_WR_CYCLES_6 (5 << 9) -VOID PL341DmcInit ( - IN PL341_DMC_CONFIG *config +VOID +PL341DmcInit ( + IN UINTN DmcBase, + IN PL341_DMC_CONFIG* DmcConfig ); VOID PL341DmcPhyInit ( |