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authoroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2011-06-11 12:10:19 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2011-06-11 12:10:19 +0000
commitf598bf12660fc7e758710e6a484d7eea3bfee6ef (patch)
treed0fdb90ed402cd870032561f71e9352e300fcd44 /ArmPlatformPkg/PrePeiCore/PrePeiCore.c
parentd6b5f236aeba4031fc9dabe553a1969e127771fe (diff)
downloadedk2-platforms-f598bf12660fc7e758710e6a484d7eea3bfee6ef.tar.xz
ArmPlatformPkg: Code cleaning
- Fix coding style to follow EDK2 coding convention - Remove deprecated function - Remove unused PCDs git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11808 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/PrePeiCore/PrePeiCore.c')
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCore.c32
1 files changed, 8 insertions, 24 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index f76a1b191f..56186471fa 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -13,29 +13,17 @@
*
**/
-#include <PiPei.h>
-#include <Ppi/TemporaryRamSupport.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
+#include <Library/PrintLib.h>
#include <Library/ArmLib.h>
+#include <Library/SerialPortLib.h>
#include <Chipset/ArmV7.h>
-EFI_STATUS
-EFIAPI
-SecTemporaryRamSupport (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- );
-
-VOID
-SecSwitchStack (
- INTN StackDelta
- );
+#include "PrePeiCore.h"
EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport};
@@ -47,10 +35,6 @@ EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = {
}
};
-// Vector Table for Pei Phase
-VOID PeiVectorTable (VOID);
-
-
VOID
CEntryPoint (
IN UINTN CoreId,
@@ -64,8 +48,8 @@ CEntryPoint (
ArmInvalidateInstructionCache();
// Enable Instruction & Data caches
- ArmEnableDataCache();
- ArmEnableInstructionCache();
+ ArmEnableDataCache ();
+ ArmEnableInstructionCache ();
//
// Note: Doesn't have to Enable CPU interface in non-secure world,
@@ -81,9 +65,9 @@ CEntryPoint (
//If not primary Jump to Secondary Main
if(0 == CoreId) {
//Goto primary Main.
- primary_main(PeiCoreEntryPoint);
+ PrimaryMain (PeiCoreEntryPoint);
} else {
- secondary_main(CoreId);
+ SecondaryMain (CoreId);
}
// PEI Core should always load and never return
@@ -101,7 +85,7 @@ SecTemporaryRamSupport (
{
//
// Migrate the whole temporary memory to permenent memory.
- //
+ //
CopyMem (
(VOID*)(UINTN)PermanentMemoryBase,
(VOID*)(UINTN)TemporaryMemoryBase,