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authoroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2012-05-02 19:55:32 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2012-05-02 19:55:32 +0000
commitb1d41be7c9c0dc18cf9b73785eee6a20f13db126 (patch)
tree6cf436c0af3f6196985ef9680972a681337de484 /ArmPlatformPkg/Sec
parentf463bb00ad63cdfbec22519c9ae878f43760e97d (diff)
downloadedk2-platforms-b1d41be7c9c0dc18cf9b73785eee6a20f13db126.tar.xz
ArmPkg/ArmCpuLib: Replaced complex functions ArmCpuSynchronizeWait & ArmCpuSynchronizeSignal by sev & wfe
Previsouly the synchronization of MpCore was using the SGI (Software Generated Interrupt) to synchronize MpCore during the early boot. This commit replaced this mechanism by the more appropriate SEV/WFE instructions (Send/Wait Event instructions). That also eases the port to a new cpu/platform. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/Sec')
-rw-r--r--ArmPlatformPkg/Sec/Sec.c13
-rw-r--r--ArmPlatformPkg/Sec/SecEntryPoint.S6
-rw-r--r--ArmPlatformPkg/Sec/SecEntryPoint.asm6
3 files changed, 13 insertions, 12 deletions
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 6939f9c6af..a8de52fcc2 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -54,7 +54,8 @@ CEntryPoint (
// Primary CPU clears out the SCU tag RAMs, secondaries wait
if (IS_PRIMARY_CORE(MpId)) {
if (ArmIsMpCore()) {
- ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
+ // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
+ ArmCallSEV ();
}
// SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
@@ -159,18 +160,18 @@ TrustedWorldInitialization (
// Setup the Trustzone Chipsets
if (IS_PRIMARY_CORE(MpId)) {
if (ArmIsMpCore()) {
- // Waiting for the Primary Core to have finished to initialize the Secure World
- ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
+ // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
+ ArmCallSEV ();
}
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
- // Waiting for the Primary Core to have finished to initialize the Secure World
- ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
+ // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
+ ArmCallWFE ();
}
- // Call the Platform specific fucntion to execute additional actions if required
+ // Call the Platform specific function to execute additional actions if required
JumpAddress = PcdGet32 (PcdFvBaseAddress);
ArmPlatformSecExtraAction (MpId, &JumpAddress);
diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.S b/ArmPlatformPkg/Sec/SecEntryPoint.S
index 42b18c40de..25b6696173 100644
--- a/ArmPlatformPkg/Sec/SecEntryPoint.S
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.S
@@ -26,7 +26,7 @@ GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
GCC_ASM_IMPORT(ArmWriteVBar)
GCC_ASM_IMPORT(ArmReadMpidr)
GCC_ASM_IMPORT(SecVectorTable)
-GCC_ASM_IMPORT(ArmCpuSynchronizeWait)
+GCC_ASM_IMPORT(ArmCallWFE)
GCC_ASM_EXPORT(_ModuleEntryPoint)
StartupAddr: .word ASM_PFX(CEntryPoint)
@@ -59,8 +59,8 @@ _IdentifyCpu:
beq _InitMem
_WaitInitMem:
- mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- bl ASM_PFX(ArmCpuSynchronizeWait)
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
+ bl ASM_PFX(ArmCallWFE)
// Now the Init Mem is initialized, we setup the secondary core stacks
b _SetupSecondaryCoreStack
diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.asm b/ArmPlatformPkg/Sec/SecEntryPoint.asm
index df443d055d..3556ce471f 100644
--- a/ArmPlatformPkg/Sec/SecEntryPoint.asm
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.asm
@@ -24,8 +24,8 @@
IMPORT ArmDisableCachesAndMmu
IMPORT ArmWriteVBar
IMPORT ArmReadMpidr
+ IMPORT ArmCallWFE
IMPORT SecVectorTable
- IMPORT ArmCpuSynchronizeWait
EXPORT _ModuleEntryPoint
PRESERVE8
@@ -61,8 +61,8 @@ _IdentifyCpu
beq _InitMem
_WaitInitMem
- mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT
- bl ArmCpuSynchronizeWait
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
+ bl ArmCallWFE
// Now the Init Mem is initialized, we setup the secondary core stacks
b _SetupSecondaryCoreStack