ArmPkg/ArmGicLib: Replaced 'ArmGicAcknowledgeSgiFrom' by 'ArmGicAcknowledgeInterrupt'

The function 'ArmGicAcknowledgeSgiFrom' was actually acknowledging Interrupts (and not only SGIs).


ArmPkg/ArmGicLib: Introduced the PCD PcdGicPrimaryCoreId

This PCD defines the Id of the primary core in the GIC.


Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13259 6f19259b-4bc3-4df7-8a09-765794883524

5 files changed, 33 insertions, 9 deletions

diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
index 6992b4a609..471a42c1ab 100755
--- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
+++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
@@ -38,7 +38,7 @@ NonSecureWaitForFirmware (
   ArmCallWFI();

 

   // Acknowledge the interrupt and send End of Interrupt signal.

-  ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);

+  ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);

 

   // Jump to secondary core entry point.

   secondary_start ();

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 01cb06f8e5..aeea8f5bda 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -45,6 +45,7 @@ SecondaryMain (
   UINT32                  CoreId;

   VOID                    (*SecondaryStart)(VOID);

   UINTN                   SecondaryEntryAddr;

+  UINTN                   AcknowledgedCoreId;

 

   ClusterId = GET_CLUSTER_ID(MpId);

   CoreId    = GET_CORE_ID(MpId);

@@ -80,12 +81,15 @@ SecondaryMain (
   // Clear Secondary cores MailBox

   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);

 

-  SecondaryEntryAddr = 0;

-  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {

+  do {

     ArmCallWFI ();

+

+    // Read the Mailbox

+    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);

+

     // Acknowledge the interrupt and send End of Interrupt signal.

-    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);

-  }

+    ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);

+  } while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));

 

   // Jump to secondary core entry point.

   SecondaryStart = (VOID (*)())SecondaryEntryAddr;

@@ -107,6 +111,13 @@ PrimaryMain (
   UINTN                       TemporaryRamBase;

   UINTN                       TemporaryRamSize;

 

+  // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0

+  DEBUG_CODE_BEGIN();

+  if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {

+    DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));

+  }

+  DEBUG_CODE_END();

+

   CreatePpiList (&PpiListSize, &PpiList);

 

   // Enable the GIC Distributor

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
index 39dd89e800..efdc4b7544 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -61,6 +61,7 @@
 

   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

   gArmTokenSpaceGuid.PcdArmPrimaryCore

+  gArmTokenSpaceGuid.PcdGicPrimaryCoreId

 

   gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase

   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index e9a3ef56a0..2c18f9f3c3 100644
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -59,6 +59,13 @@ PrimaryMain (
     ASSERT_EFI_ERROR (Status);

   DEBUG_CODE_END();

 

+  // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0

+  DEBUG_CODE_BEGIN();

+  if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {

+    DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));

+  }

+  DEBUG_CODE_END();

+

   // Enable the GIC Distributor

   ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));

 

@@ -88,6 +95,7 @@ SecondaryMain (
   UINT32                  CoreId;

   VOID                    (*SecondaryStart)(VOID);

   UINTN                   SecondaryEntryAddr;

+  UINTN                   AcknowledgedCoreId;

 

   ClusterId = GET_CLUSTER_ID(MpId);

   CoreId    = GET_CORE_ID(MpId);

@@ -113,12 +121,15 @@ SecondaryMain (
   // Clear Secondary cores MailBox

   MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);

 

-  SecondaryEntryAddr = 0;

-  while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {

+  do {

     ArmCallWFI ();

+

+    // Read the Mailbox

+    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);

+

     // Acknowledge the interrupt and send End of Interrupt signal.

-    ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);

-  }

+    ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);

+  } while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));

 

   // Jump to secondary core entry point.

   SecondaryStart = (VOID (*)())SecondaryEntryAddr;

diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiMPCore.inf
index 6337da1334..12789a3965 100755
--- a/ArmPlatformPkg/PrePi/PeiMPCore.inf
+++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf
@@ -94,6 +94,7 @@
   gArmPlatformTokenSpaceGuid.PcdClusterCount

   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

   gArmTokenSpaceGuid.PcdArmPrimaryCore

+  gArmTokenSpaceGuid.PcdGicPrimaryCoreId

 

   gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize

   gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize