diff options
| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 15:30:01 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 15:30:01 +0000 |
| commit | 5cc45b70c310f853f28b2351f3d93109ff858dcf (patch) | |
| tree | 22917c5dfa20a9f553c1adda9ce6efc04b722dc7 /ArmPlatformPkg | |
| parent | 7fb54d9d04f52e22f6df16e0035c565c3dce7bd4 (diff) | |
| download | edk2-platforms-5cc45b70c310f853f28b2351f3d93109ff858dcf.tar.xz | |
ArmPkg: Move ARM Platform drivers from ArmPkg/Drivers/ to ArmPlatformPkg/Drivers/
The idea is to keep ArmPkg responsible for the ARM architectural modules and ArmPlatformPkg
the ARM development platform packages (with their respective drivers).
ArmPlatformPkg: Reduce driver dependency on ArmPlatform.h
- Move some driver definitions from C-Macro to PCD values
- Unify PCD driver namespace
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11956 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg')
48 files changed, 895 insertions, 363 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 2a5c15e4b5..a332f2cca3 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -77,8 +77,36 @@ # # ARM Primecells # - gArmPlatformTokenSpaceGuid.PcdSP804FrequencyInMHz|1|UINT32|0x0000001D - gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|0|UINT32|0x0000001E + + ## SP804 DualTimer + gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C + + ## SP805 Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023 + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021 + + ## PL011 UART + gArmPlatformTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0x00000000|UINT32|0x0000001F + gArmPlatformTokenSpaceGuid.PcdUartDefaultTimeout|0x00000000|UINT32|0x00000020 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 + gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022 + + ## PL061 GPIO + gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025 + + ## PL111 Lcd + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 + + ## PL180 MCI + gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028 + gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029 # # BDS - Boot Manager diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc index f86730cbb9..4883e511f5 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc @@ -132,7 +132,7 @@ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
# L2 Cache Driver
- L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
+ L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
@@ -357,11 +357,7 @@ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
-
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
- gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
- gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|36
-
+
#
# ARM Pcds
#
@@ -373,6 +369,24 @@ gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000
#
+ # ARM PrimeCells
+ #
+
+ ## SP804 Timer
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|36
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x10011000
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x10012020
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x10012000
+
+ ## PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x10017000
+
+ ## PL111 Lcd
+ gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x10020000
+
+ #
# ARM PL011 - Serial Terminal
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10009000
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc index 64f5b552cd..7ae4ccd2fa 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc +++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc @@ -133,7 +133,7 @@ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf # L2 Cache Driver - L2X0CacheLib|ArmPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf + L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf # ARM PL390 General Interrupt Driver in Secure and Non-secure PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf @@ -360,11 +360,7 @@ # Size of the region used by UEFI in permanent memory (Reserved 64MB) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 - - gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 - gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms - gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|33 - + # # ARM Pcds # @@ -376,6 +372,21 @@ gArmRealViewEbPkgTokenSpaceGuid.PcdGdbUartBase|0x1000a000 # + # ARM PrimeCells + # + + ## SP804 Timer + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|33 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x10011000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x10012020 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x10012000 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x10017000 + + # # ARM PL011 - Serial Terminal # gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10009000 diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h b/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h index 04e1ce86d4..cc76bb20de 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform/ArmPlatform.h @@ -120,10 +120,6 @@ //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
-// PL031 RTC - Other settings
-#define PL031_PPM_ACCURACY 300000000
-
-
/*******************************************
// EFI Memory Map in Permanent Memory (DRAM)
*******************************************/
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c index 8a1446a81d..5709ca6c01 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEb.c @@ -20,6 +20,8 @@ #include <Drivers/PL341Dmc.h> #include <Drivers/SP804Timer.h> +#include <ArmPlatform.h> + /** Return if Trustzone is supported by your platform @@ -102,7 +104,7 @@ ArmPlatformSecInitialize ( /** Initialize controllers that must setup in the normal world - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei in the PEI phase. **/ diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c index 616fa0ef8c..a5489d06a8 100644 --- a/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c +++ b/ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbMem.c @@ -18,6 +18,8 @@ #include <Library/MemoryAllocationLib.h>
#include <Library/IoLib.h>
+#include <ArmPlatform.h>
+
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6
// DDR attributes
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc index 48c64b1cba..303c0183af 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc @@ -95,13 +95,13 @@ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf # ARM PL310 L2 Cache Driver - L2X0CacheLib|ArmPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf + L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf # ARM PL354 SMC Driver - PL354SmcLib|ArmPkg/Drivers/PL35xSmc/PL354SmcSec.inf + PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf # ARM PL341 DMC Driver - PL341DmcLib|ArmPkg/Drivers/PL34xDmc/PL341Dmc.inf + PL341DmcLib|ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.inf # ARM PL301 Axi Driver - PL301AxiLib|ArmPkg/Drivers/PL301Axi/PL301Axi.inf + PL301AxiLib|ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.inf # ARM PL011 UART Driver PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf @@ -392,27 +392,45 @@ # System Memory (1GB) gArmTokenSpaceGuid.PcdSystemMemoryBase|0x60000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 - - gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 - gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms - gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum|34 - + # # ARM Pcds # gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 - + # # ARM PrimeCell # - gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x10000048 - gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000 - # - # ARM PL011 - Serial Terminal - # + ## SP804 Timer + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|34 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x10011000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x10012020 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x10012000 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1000F000 + ## SP805 Watchdog - CoreTile Watchdog + #gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x100E5000 + + ## PL011 - Serial Terminal gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10009000 gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x10017000 + + ## PL111 Lcd + # PL111 CoreTile or Tuscan Standalone controller + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x10020000 + # PL111 Versatile Express Motherboard controller + #gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1001F000 + + ## PL180 MMC/SD card controller + gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x10000048 + gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x10005000 # # ARM PL390 General Interrupt Controller @@ -532,7 +550,7 @@ # Multimedia Card Interface # EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf - ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf # # FAT filesystem + GPT/MBR partitioning diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf index 6781f5e974..3cdf9d5ef7 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf @@ -187,7 +187,7 @@ READ_LOCK_STATUS = TRUE # Multimedia Card Interface # INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf - INF ArmPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf # # UEFI application (Shell Embedded Boot Loader) diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec index 307e672cd0..12c57101b1 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec @@ -47,4 +47,5 @@ # # For a list of mode numbers look in LcdArmVExpress.c # - gArmVExpressTokenSpaceGuid.PcdPL111MaxMode|3|UINT32|0x00000003 + gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000003 + gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000004 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h index 171b0420d5..e11e9c7d19 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4/ArmPlatform.h @@ -52,10 +52,10 @@ #define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
// DRAM
-#define ARM_VE_DRAM_BASE 0x60000000
-#define ARM_VE_DRAM_SZ 0x40000000
+#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)
+#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)
// Inside the DRAM we allocate a section for the VRAM (Video RAM)
-#define LCD_VRAM_CORE_TILE_BASE 0x64000000
+#define LCD_VRAM_CORE_TILE_BASE 0x64000000
// External AXI between daughterboards (Logic Tile)
#define ARM_VE_EXT_AXI_BASE 0xE0000000
@@ -99,18 +99,6 @@ //#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000
/***********************************************************************************
- Select between Motherboard and Core Tile peripherals
-************************************************************************************/
-
-// Specify which PL111 to use
-//#define PL111_CLCD_BASE PL111_CLCD_MOTHERBOARD_BASE
-#define PL111_CLCD_BASE PL111_CLCD_CORE_TILE_BASE
-
-// Specify which Watchdog to use
-#define SP805_WDOG_BASE SP805_WDOG_MOTHERBOARD_BASE
-//#define SP805_WDOG_BASE SP805_WDOG_CORE_TILE_BASE
-
-/***********************************************************************************
Peripherals' misc settings
************************************************************************************/
@@ -130,16 +118,6 @@ #define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)
-// PL031 RTC - Other settings
-#define PL031_PPM_ACCURACY 300000000
-
-// SP805 Watchdog - Other settings
-#define SP805_CLOCK_FREQUENCY 32000
-#define SP805_MAX_TICKS 0xFFFFFFFF
-
-// PL111 Lcd
-#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
-
/***********************************************************************************
// EFI Memory Map in Permanent Memory (DRAM)
************************************************************************************/
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf index d78f631829..5670fab7c4 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf @@ -50,4 +50,7 @@ [FixedPcd] gArmPlatformTokenSpaceGuid.PcdStandalone + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdL2x0ControllerBase diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c index c72a5a4cba..17d09a605a 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c @@ -23,6 +23,8 @@ #include <Drivers/PL301Axi.h> #include <Drivers/SP804Timer.h> +#include <ArmPlatform.h> + #define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1); // DDR2 timings @@ -121,7 +123,7 @@ ArmPlatformBootRemapping ( /** Initialize controllers that must setup in the normal world - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei in the PEI phase. **/ diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c index eed01ed7ef..7bfd679411 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Mem.c @@ -18,6 +18,8 @@ #include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <ArmPlatform.h>
+
// Number of Virtual Memory Map Descriptors without a Logic Tile
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Sec.c index 2ac64a0160..46ca8eaac4 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Sec.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Sec.c @@ -21,6 +21,8 @@ #include <Drivers/PL310L2Cache.h> +#include <ArmPlatform.h> + /** Initialize the Secure peripherals and memory regions diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf index 01027cc271..5e06063185 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf @@ -31,6 +31,7 @@ [LibraryClasses] BaseLib + IoLib [Guids] diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c index 6ae5da9997..8198dfd5cd 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c @@ -195,7 +195,7 @@ LcdPlatformGetMaxMode ( // This could be because the specific implementation of PL111 has certain limitations.
// Set the maximum mode allowed
- return (PcdGet32(PcdPL111MaxMode));
+ return (PcdGet32(PcdPL111LcdMaxMode));
}
EFI_STATUS
@@ -221,7 +221,7 @@ LcdPlatformSetMode ( break;
case ARM_VE_DAUGHTERBOARD_1_SITE:
Function = SYS_CFG_OSC_SITE1;
- OscillatorId = PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID;
+ OscillatorId = (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId);
break;
default:
return EFI_UNSUPPORTED;
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf index 6edca3ba09..eca42752b5 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf @@ -33,15 +33,6 @@ BaseLib ArmPlatformSysConfigLib -[Guids] - -[Protocols] - -[FeaturePcd] - -[FixedPcd.common] - gArmVExpressTokenSpaceGuid.PcdPL111MaxMode - -[Pcd.common] - -[Depex] +[Pcd] + gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode + gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c index 679ccc8256..b341c5e7b9 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c @@ -22,7 +22,6 @@ #include <Guid/GlobalVariable.h> -#include <ArmPlatform.h> #include "LcdGraphicsOutputDxe.h" extern BOOLEAN mDisplayInitialized; diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c index a4ab6a68f5..8c9165e730 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -13,7 +13,6 @@ #include <PiDxe.h> #include <Library/PcdLib.h> -#include <Library/DebugLib.h> #include <Library/BaseMemoryLib.h> #include <Library/DevicePathLib.h> #include <Library/UefiBootServicesTableLib.h> @@ -22,7 +21,6 @@ #include <Guid/GlobalVariable.h> -#include <ArmPlatform.h> #include "LcdGraphicsOutputDxe.h" /********************************************************************** diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf index ae571d8d83..668c24472f 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf @@ -45,16 +45,12 @@ BaseMemoryLib LcdPlatformLib -[Guids] - [Protocols] gEfiDevicePathProtocolGuid gEfiGraphicsOutputProtocolGuid -[FixedPcd.common] - -[Pcd.common] - +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase [Depex] gEfiCpuArchProtocolGuid diff --git a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.h b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.h index 60cdbd5a43..5abf8fccf6 100644 --- a/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.h +++ b/ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.h @@ -26,8 +26,6 @@ #include <Library/NorFlashPlatformLib.h> #include <Library/UefiLib.h> -#include <ArmPlatform.h> - #define HIGH_16_BITS 0xFFFF0000 #define LOW_16_BITS 0x0000FFFF #define LOW_8_BITS 0x000000FF diff --git a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c index 0e263c03a7..cb811d89d6 100644 --- a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c +++ b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c @@ -13,23 +13,20 @@ **/ -#include <Base.h> #include <PiDxe.h> #include <Library/BaseLib.h> -#include <Library/DebugLib.h> #include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> #include <Library/UefiBootServicesTableLib.h> -#include <Library/UefiRuntimeServicesTableLib.h> #include <Library/UefiLib.h> -#include <Library/IoLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> #include <Protocol/EmbeddedGpio.h> -#include <ArmPlatform.h> #include <Drivers/PL061Gpio.h> -#define LOW_4_BITS 0x0000000F - BOOLEAN mPL061Initialized = FALSE; /** @@ -42,18 +39,18 @@ PL061Identify ( ) { // Check if this is a PrimeCell Peripheral - if( ( MmioRead8( PL061_GPIO_PCELL_ID0 ) != 0x0D ) - || ( MmioRead8( PL061_GPIO_PCELL_ID1 ) != 0xF0 ) - || ( MmioRead8( PL061_GPIO_PCELL_ID2 ) != 0x05 ) - || ( MmioRead8( PL061_GPIO_PCELL_ID3 ) != 0xB1 ) ) { + if ( (MmioRead8 (PL061_GPIO_PCELL_ID0) != 0x0D) + || (MmioRead8 (PL061_GPIO_PCELL_ID1) != 0xF0) + || (MmioRead8 (PL061_GPIO_PCELL_ID2) != 0x05) + || (MmioRead8 (PL061_GPIO_PCELL_ID3) != 0xB1)) { return EFI_NOT_FOUND; } // Check if this PrimeCell Peripheral is the PL061 GPIO - if( ( MmioRead8( PL061_GPIO_PERIPH_ID0 ) != 0x61 ) - || ( MmioRead8( PL061_GPIO_PERIPH_ID1 ) != 0x10 ) - || ( ( MmioRead8( PL061_GPIO_PERIPH_ID2 ) & LOW_4_BITS ) != 0x04 ) - || ( MmioRead8( PL061_GPIO_PERIPH_ID3 ) != 0x00 ) ) { + if ( (MmioRead8 (PL061_GPIO_PERIPH_ID0) != 0x61) + || (MmioRead8 (PL061_GPIO_PERIPH_ID1) != 0x10) + || ((MmioRead8 (PL061_GPIO_PERIPH_ID2) & 0xF) != 0x04) + || (MmioRead8 (PL061_GPIO_PERIPH_ID3) != 0x00)) { return EFI_NOT_FOUND; } @@ -62,14 +59,14 @@ PL061Identify ( EFI_STATUS PL061Initialize ( -VOID + VOID ) { EFI_STATUS Status; // Check if the PL061 GPIO module exists on board Status = PL061Identify(); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { Status = EFI_DEVICE_ERROR; goto EXIT; } @@ -77,7 +74,7 @@ VOID // Do other hardware initialisation things here as required // Disable Interrupts - //if( MmioRead8( PL061_GPIO_IE_REG ) != 0 ) { + //if (MmioRead8 (PL061_GPIO_IE_REG) != 0) { // // Ensure interrupts are disabled //} @@ -114,21 +111,21 @@ Get ( { EFI_STATUS Status = EFI_SUCCESS; - if( ( Value == NULL ) - || ( Gpio > LAST_GPIO_PIN ) ) + if ( (Value == NULL) + || (Gpio > LAST_GPIO_PIN)) { return EFI_INVALID_PARAMETER; } // Initialize the hardware if not already done - if( !mPL061Initialized ) { + if (!mPL061Initialized) { Status = PL061Initialize(); - if( EFI_ERROR(Status) ) { + if (EFI_ERROR(Status)) { goto EXIT; } } - if( MmioRead8( PL061_GPIO_DATA_REG ) & GPIO_PIN_MASK_HIGH_8BIT(Gpio) ) { + if (MmioRead8 (PL061_GPIO_DATA_REG) & GPIO_PIN_MASK_HIGH_8BIT(Gpio)) { *Value = 1; } else { *Value = 0; @@ -167,15 +164,15 @@ Set ( EFI_STATUS Status = EFI_SUCCESS; // Check for errors - if( Gpio > LAST_GPIO_PIN ) { + if (Gpio > LAST_GPIO_PIN) { Status = EFI_INVALID_PARAMETER; goto EXIT; } // Initialize the hardware if not already done - if( !mPL061Initialized ) { + if (!mPL061Initialized) { Status = PL061Initialize(); - if( EFI_ERROR(Status) ) { + if (EFI_ERROR(Status)) { goto EXIT; } } @@ -184,21 +181,21 @@ Set ( { case GPIO_MODE_INPUT: // Set the corresponding direction bit to LOW for input - MmioAnd8( PL061_GPIO_DIR_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio) ); + MmioAnd8 (PL061_GPIO_DIR_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio)); break; case GPIO_MODE_OUTPUT_0: // Set the corresponding data bit to LOW for 0 - MmioAnd8( PL061_GPIO_DATA_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio) ); + MmioAnd8 (PL061_GPIO_DATA_REG, GPIO_PIN_MASK_LOW_8BIT(Gpio)); // Set the corresponding direction bit to HIGH for output - MmioOr8( PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio) ); + MmioOr8 (PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio)); break; case GPIO_MODE_OUTPUT_1: // Set the corresponding data bit to HIGH for 1 - MmioOr8( PL061_GPIO_DATA_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio) ); + MmioOr8 (PL061_GPIO_DATA_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio)); // Set the corresponding direction bit to HIGH for output - MmioOr8( PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio) ); + MmioOr8 (PL061_GPIO_DIR_REG, GPIO_PIN_MASK_HIGH_8BIT(Gpio)); break; default: @@ -239,23 +236,23 @@ GetMode ( EFI_STATUS Status; // Check for errors - if( ( Mode == NULL ) - || ( Gpio > LAST_GPIO_PIN ) ) { + if ( (Mode == NULL) + || (Gpio > LAST_GPIO_PIN)) { return EFI_INVALID_PARAMETER; } // Initialize the hardware if not already done - if( !mPL061Initialized ) { + if (!mPL061Initialized) { Status = PL061Initialize(); - if( EFI_ERROR(Status) ) { + if (EFI_ERROR(Status)) { return Status; } } // Check if it is input or output - if( MmioRead8( PL061_GPIO_DIR_REG ) & GPIO_PIN_MASK_HIGH_8BIT(Gpio) ) { + if (MmioRead8 (PL061_GPIO_DIR_REG) & GPIO_PIN_MASK_HIGH_8BIT(Gpio)) { // Pin set to output - if( MmioRead8( PL061_GPIO_DATA_REG ) & GPIO_PIN_MASK_HIGH_8BIT(Gpio) ) { + if (MmioRead8 (PL061_GPIO_DATA_REG) & GPIO_PIN_MASK_HIGH_8BIT(Gpio)) { *Mode = GPIO_MODE_OUTPUT_1; } else { *Mode = GPIO_MODE_OUTPUT_0; @@ -338,7 +335,7 @@ PL061InstallProtocol ( &Handle, &gEmbeddedGpioProtocolGuid, &gGpio, NULL - ); + ); if (EFI_ERROR(Status)) { Status = EFI_OUT_OF_RESOURCES; } diff --git a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf index 53eebdaec9..b5adda3a89 100644 --- a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf +++ b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf @@ -31,19 +31,20 @@ [LibraryClasses] BaseLib - UefiRuntimeServicesTableLib - UefiLib - UefiBootServicesTableLib BaseMemoryLib DebugLib - UefiDriverEntryPoint IoLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib -[Guids] +[Pcd] + gArmPlatformTokenSpaceGuid.PcdPL061GpioBase [Protocols] gEmbeddedGpioProtocolGuid - [Depex] -TRUE + TRUE diff --git a/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c b/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c index e74b7e1382..159e9256a1 100644 --- a/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c +++ b/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804Timer.c @@ -28,7 +28,10 @@ #include <Protocol/HardwareInterrupt.h> #include <Drivers/SP804Timer.h> -#include <ArmPlatform.h> + +#define SP804_TIMER_PERIODIC_BASE (UINTN)PcdGet32 (PcdSP804TimerPeriodicBase) +#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase) +#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase) // The notification function to call on every timer interrupt. volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL; @@ -43,7 +46,6 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; // Cached interrupt vector UINTN gVector; -UINT32 mLastTickCount; /** @@ -75,9 +77,9 @@ TimerInterruptHandler ( OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); // If the interrupt is shared then we must check if this interrupt source is the one associated to this Timer - if (MmioRead32 (SP804_TIMER0_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) { + if (MmioRead32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_MSK_INT_STS_REG) != 0) { // clear the periodic interrupt - MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_INT_CLR_REG, 0); + MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_INT_CLR_REG, 0); // signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers gInterrupt->EndOfInterrupt (gInterrupt, Source); @@ -139,7 +141,7 @@ TimerDriverRegisterHandler ( } /** - Make sure all ArrmVe Timers are disabled + Make sure all Dual Timers are disabled **/ VOID EFIAPI @@ -148,25 +150,20 @@ ExitBootServicesEvent ( IN VOID *Context ) { - // Disable timer 0 if enabled - if (MmioRead32(SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { - MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, 0); - } - - // Disable timer 1 if enabled - if (MmioRead32(SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { - MmioAnd32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, 0); - } + // Disable 'Periodic Operation' timer if enabled + if (MmioRead32(SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { + MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, 0); + } - // Disable timer 2 if enabled - if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { - MmioAnd32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, 0); - } + // Disable 'Metronome/Delay' timer if enabled + if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { + MmioAnd32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, 0); + } - // Disable timer 3 if enabled - if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { - MmioAnd32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, 0); - } + // Disable 'Performance' timer if enabled + if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { + MmioAnd32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, 0); + } } /** @@ -208,7 +205,7 @@ TimerDriverSetTimerPeriod ( UINT64 TimerTicks; // always disable the timer - MmioAnd32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE); + MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE); if (TimerPeriod == 0) { // Leave timer disabled from above, and... @@ -218,7 +215,7 @@ TimerDriverSetTimerPeriod ( } else { // Convert TimerPeriod into 1MHz clock counts (us units = 100ns units / 10) TimerTicks = DivU64x32 (TimerPeriod, 10); - TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804FrequencyInMHz)); + TimerTicks = MultU64x32 (TimerTicks, PcdGet32(PcdSP804TimerFrequencyInMHz)); // if it's larger than 32-bits, pin to highest value if (TimerTicks > 0xffffffff) { @@ -228,10 +225,10 @@ TimerDriverSetTimerPeriod ( } // Program the SP804 timer with the new count value - MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_LOAD_REG, TimerTicks); + MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_LOAD_REG, TimerTicks); // enable the timer - MmioOr32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); + MmioOr32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); // enable timer 0/1 interrupts Status = gInterrupt->EnableInterruptSource (gInterrupt, gVector); @@ -365,26 +362,17 @@ TimerInitialize ( Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt); ASSERT_EFI_ERROR (Status); - // Configure timer 1 for free running operation, 32 bits, no prescaler, interrupt disabled - MmioWrite32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); - - // Enable the free running timer - MmioOr32 (SP804_TIMER1_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); - - // Record free running tick value (should be close to 0xffffffff) - mLastTickCount = MmioRead32 (SP804_TIMER1_BASE + SP804_TIMER_CURRENT_REG); - // Disable the timer Status = TimerDriverSetTimerPeriod (&gTimer, 0); ASSERT_EFI_ERROR (Status); // Install interrupt handler - gVector = PcdGet32(PcdSP804Timer0InterruptNum); + gVector = PcdGet32(PcdSP804TimerPeriodicInterruptNum); Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler); ASSERT_EFI_ERROR (Status); // configure timer 0 for periodic operation, 32 bits, no prescaler, and interrupt enabled - MmioWrite32 (SP804_TIMER0_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE); + MmioWrite32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_PERIODIC | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1 | SP804_TIMER_CTRL_INT_ENABLE); // Set up default timer Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD diff --git a/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf b/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf index 017277ad71..f314fb1a0b 100644 --- a/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf +++ b/ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf @@ -48,8 +48,11 @@ gHardwareInterruptProtocolGuid [Pcd.common] - gArmPlatformTokenSpaceGuid.PcdSP804FrequencyInMHz - gArmPlatformTokenSpaceGuid.PcdSP804Timer0InterruptNum + gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase gEmbeddedTokenSpaceGuid.PcdTimerPeriod [Depex] diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c index 0eb459303f..840f8ede1f 100644 --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c @@ -16,15 +16,15 @@ #include <PiDxe.h> #include <Library/BaseLib.h> -#include <Library/DebugLib.h> #include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> #include <Library/UefiBootServicesTableLib.h> #include <Library/UefiRuntimeServicesTableLib.h> #include <Library/UefiLib.h> -#include <Library/IoLib.h> #include <Protocol/WatchdogTimer.h> -#include <ArmPlatform.h> #include <Drivers/SP805Watchdog.h> /** @@ -75,18 +75,18 @@ SP805Identify ( ) { // Check if this is a PrimeCell Peripheral - if( ( MmioRead8( SP805_WDOG_PCELL_ID0 ) != 0x0D ) - || ( MmioRead8( SP805_WDOG_PCELL_ID1 ) != 0xF0 ) - || ( MmioRead8( SP805_WDOG_PCELL_ID2 ) != 0x05 ) - || ( MmioRead8( SP805_WDOG_PCELL_ID3 ) != 0xB1 ) ) { + if ( (MmioRead8 (SP805_WDOG_PCELL_ID0) != 0x0D) + || (MmioRead8 (SP805_WDOG_PCELL_ID1) != 0xF0) + || (MmioRead8 (SP805_WDOG_PCELL_ID2) != 0x05) + || (MmioRead8 (SP805_WDOG_PCELL_ID3) != 0xB1)) { return EFI_NOT_FOUND; } // Check if this PrimeCell Peripheral is the SP805 Watchdog Timer - if( ( MmioRead8( SP805_WDOG_PERIPH_ID0 ) != 0x05 ) - || ( MmioRead8( SP805_WDOG_PERIPH_ID1 ) != 0x18 ) - || (( MmioRead8( SP805_WDOG_PERIPH_ID2 ) & 0x0000000F) != 0x04 ) - || ( MmioRead8( SP805_WDOG_PERIPH_ID3 ) != 0x00 ) ) { + if ( (MmioRead8 (SP805_WDOG_PERIPH_ID0) != 0x05) + || (MmioRead8 (SP805_WDOG_PERIPH_ID1) != 0x18) + || ((MmioRead8 (SP805_WDOG_PERIPH_ID2) & 0x0000000F) != 0x04) + || (MmioRead8 (SP805_WDOG_PERIPH_ID3) != 0x00)) { return EFI_NOT_FOUND; } diff --git a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf index b77320120c..7cacf69f4f 100644 --- a/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf +++ b/ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf @@ -32,19 +32,21 @@ [LibraryClasses] BaseLib - UefiRuntimeServicesTableLib - UefiLib - UefiBootServicesTableLib BaseMemoryLib DebugLib - UefiDriverEntryPoint IoLib + PcdLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib -[Guids] +[Pcd] + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz [Protocols] gEfiWatchdogTimerArchProtocolGuid - [Depex] -TRUE + TRUE diff --git a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h index 8c26d66053..4c559c0c95 100644 --- a/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h +++ b/ArmPlatformPkg/Include/Drivers/PL031RealTimeClock.h @@ -16,26 +16,23 @@ #ifndef __PL031_REAL_TIME_CLOCK_H__
#define __PL031_REAL_TIME_CLOCK_H__
-#include <Base.h>
-#include <ArmPlatform.h>
-
// PL031 Registers
-#define PL031_RTC_DR_DATA_REGISTER (PL031_RTC_BASE + 0x000)
-#define PL031_RTC_MR_MATCH_REGISTER (PL031_RTC_BASE + 0x004)
-#define PL031_RTC_LR_LOAD_REGISTER (PL031_RTC_BASE + 0x008)
-#define PL031_RTC_CR_CONTROL_REGISTER (PL031_RTC_BASE + 0x00C)
-#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER (PL031_RTC_BASE + 0x010)
-#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER (PL031_RTC_BASE + 0x014)
-#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER (PL031_RTC_BASE + 0x018)
-#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER (PL031_RTC_BASE + 0x01C)
-#define PL031_RTC_PERIPH_ID0 (PL031_RTC_BASE + 0xFE0)
-#define PL031_RTC_PERIPH_ID1 (PL031_RTC_BASE + 0xFE4)
-#define PL031_RTC_PERIPH_ID2 (PL031_RTC_BASE + 0xFE8)
-#define PL031_RTC_PERIPH_ID3 (PL031_RTC_BASE + 0xFEC)
-#define PL031_RTC_PCELL_ID0 (PL031_RTC_BASE + 0xFF0)
-#define PL031_RTC_PCELL_ID1 (PL031_RTC_BASE + 0xFF4)
-#define PL031_RTC_PCELL_ID2 (PL031_RTC_BASE + 0xFF8)
-#define PL031_RTC_PCELL_ID3 (PL031_RTC_BASE + 0xFFC)
+#define PL031_RTC_DR_DATA_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x000)
+#define PL031_RTC_MR_MATCH_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x004)
+#define PL031_RTC_LR_LOAD_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x008)
+#define PL031_RTC_CR_CONTROL_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x00C)
+#define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x010)
+#define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x014)
+#define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x018)
+#define PL031_RTC_ICR_IRQ_CLEAR_REGISTER ((UINT32)PcdGet32(PcdPL031RtcBase) + 0x01C)
+#define PL031_RTC_PERIPH_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE0)
+#define PL031_RTC_PERIPH_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE4)
+#define PL031_RTC_PERIPH_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFE8)
+#define PL031_RTC_PERIPH_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFEC)
+#define PL031_RTC_PCELL_ID0 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF0)
+#define PL031_RTC_PCELL_ID1 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF4)
+#define PL031_RTC_PCELL_ID2 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFF8)
+#define PL031_RTC_PCELL_ID3 ((UINT32)PcdGet32(PcdPL031RtcBase) + 0xFFC)
// PL031 Values
#define PL031_RTC_ENABLED 0x00000001
diff --git a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h index 4daabff768..739caaf2a1 100644 --- a/ArmPlatformPkg/Include/Drivers/PL061Gpio.h +++ b/ArmPlatformPkg/Include/Drivers/PL061Gpio.h @@ -16,31 +16,29 @@ #ifndef __PL061_GPIO_H__
#define __PL061_GPIO_H__
-#include <Base.h>
#include <Protocol/EmbeddedGpio.h>
-#include <ArmPlatform.h>
// SP805 Watchdog Registers
-#define PL061_GPIO_DATA_REG (PL061_GPIO_BASE + 0x000)
-#define PL061_GPIO_DIR_REG (PL061_GPIO_BASE + 0x400)
-#define PL061_GPIO_IS_REG (PL061_GPIO_BASE + 0x404)
-#define PL061_GPIO_IBE_REG (PL061_GPIO_BASE + 0x408)
-#define PL061_GPIO_IEV_REG (PL061_GPIO_BASE + 0x40C)
-#define PL061_GPIO_IE_REG (PL061_GPIO_BASE + 0x410)
-#define PL061_GPIO_RIS_REG (PL061_GPIO_BASE + 0x414)
-#define PL061_GPIO_MIS_REG (PL061_GPIO_BASE + 0x410)
-#define PL061_GPIO_IC_REG (PL061_GPIO_BASE + 0x41C)
-#define PL061_GPIO_AFSEL_REG (PL061_GPIO_BASE + 0x420)
-
-#define PL061_GPIO_PERIPH_ID0 (PL061_GPIO_BASE + 0xFE0)
-#define PL061_GPIO_PERIPH_ID1 (PL061_GPIO_BASE + 0xFE4)
-#define PL061_GPIO_PERIPH_ID2 (PL061_GPIO_BASE + 0xFE8)
-#define PL061_GPIO_PERIPH_ID3 (PL061_GPIO_BASE + 0xFEC)
-
-#define PL061_GPIO_PCELL_ID0 (PL061_GPIO_BASE + 0xFF0)
-#define PL061_GPIO_PCELL_ID1 (PL061_GPIO_BASE + 0xFF4)
-#define PL061_GPIO_PCELL_ID2 (PL061_GPIO_BASE + 0xFF8)
-#define PL061_GPIO_PCELL_ID3 (PL061_GPIO_BASE + 0xFFC)
+#define PL061_GPIO_DATA_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x000)
+#define PL061_GPIO_DIR_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x400)
+#define PL061_GPIO_IS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x404)
+#define PL061_GPIO_IBE_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x408)
+#define PL061_GPIO_IEV_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x40C)
+#define PL061_GPIO_IE_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)
+#define PL061_GPIO_RIS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x414)
+#define PL061_GPIO_MIS_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x410)
+#define PL061_GPIO_IC_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x41C)
+#define PL061_GPIO_AFSEL_REG ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0x420)
+
+#define PL061_GPIO_PERIPH_ID0 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE0)
+#define PL061_GPIO_PERIPH_ID1 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE4)
+#define PL061_GPIO_PERIPH_ID2 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFE8)
+#define PL061_GPIO_PERIPH_ID3 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFEC)
+
+#define PL061_GPIO_PCELL_ID0 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF0)
+#define PL061_GPIO_PCELL_ID1 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF4)
+#define PL061_GPIO_PCELL_ID2 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFF8)
+#define PL061_GPIO_PCELL_ID3 ((UINT32)PcdGet32 (PcdPL061GpioBase) + 0xFFC)
// GPIO pins are numbered 0..7
diff --git a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h b/ArmPlatformPkg/Include/Drivers/PL111Lcd.h index 80d563976d..d68acd83b3 100644 --- a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h +++ b/ArmPlatformPkg/Include/Drivers/PL111Lcd.h @@ -14,8 +14,6 @@ #ifndef _PL111LCD_H__ #define _PL111LCD_H__ -#include <ArmPlatform.h> - /********************************************************************** * * This header file contains all the bits of the PL111 that are @@ -24,30 +22,30 @@ **********************************************************************/ // Controller Register Offsets -#define PL111_REG_LCD_TIMING_0 (PL111_CLCD_BASE + 0x000) -#define PL111_REG_LCD_TIMING_1 (PL111_CLCD_BASE + 0x004) -#define PL111_REG_LCD_TIMING_2 (PL111_CLCD_BASE + 0x008) -#define PL111_REG_LCD_TIMING_3 (PL111_CLCD_BASE + 0x00C) -#define PL111_REG_LCD_UP_BASE (PL111_CLCD_BASE + 0x010) -#define PL111_REG_LCD_LP_BASE (PL111_CLCD_BASE + 0x014) -#define PL111_REG_LCD_CONTROL (PL111_CLCD_BASE + 0x018) -#define PL111_REG_LCD_IMSC (PL111_CLCD_BASE + 0x01C) -#define PL111_REG_LCD_RIS (PL111_CLCD_BASE + 0x020) -#define PL111_REG_LCD_MIS (PL111_CLCD_BASE + 0x024) -#define PL111_REG_LCD_ICR (PL111_CLCD_BASE + 0x028) -#define PL111_REG_LCD_UP_CURR (PL111_CLCD_BASE + 0x02C) -#define PL111_REG_LCD_LP_CURR (PL111_CLCD_BASE + 0x030) -#define PL111_REG_LCD_PALETTE (PL111_CLCD_BASE + 0x200) +#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) +#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) +#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) +#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) +#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) +#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) +#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) +#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) +#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) +#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) +#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) +#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) +#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) +#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) // Identification Register Offsets -#define PL111_REG_CLCD_PERIPH_ID_0 (PL111_CLCD_BASE + 0xFE0) -#define PL111_REG_CLCD_PERIPH_ID_1 (PL111_CLCD_BASE + 0xFE4) -#define PL111_REG_CLCD_PERIPH_ID_2 (PL111_CLCD_BASE + 0xFE8) -#define PL111_REG_CLCD_PERIPH_ID_3 (PL111_CLCD_BASE + 0xFEC) -#define PL111_REG_CLCD_P_CELL_ID_0 (PL111_CLCD_BASE + 0xFF0) -#define PL111_REG_CLCD_P_CELL_ID_1 (PL111_CLCD_BASE + 0xFF4) -#define PL111_REG_CLCD_P_CELL_ID_2 (PL111_CLCD_BASE + 0xFF8) -#define PL111_REG_CLCD_P_CELL_ID_3 (PL111_CLCD_BASE + 0xFFC) +#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) +#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) +#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) +#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) +#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) +#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) +#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) +#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) /**********************************************************************/ diff --git a/ArmPlatformPkg/Include/Drivers/PL301Axi.h b/ArmPlatformPkg/Include/Drivers/PL301Axi.h new file mode 100644 index 0000000000..1bf936ff78 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/PL301Axi.h @@ -0,0 +1,21 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef PL301AXI_H_ +#define PL301AXI_H_ + +VOID PL301AxiInit(UINTN FAxiBase); + + +#endif /* PL301AXI_H_ */ diff --git a/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h b/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h new file mode 100644 index 0000000000..a610998062 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h @@ -0,0 +1,79 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef L2CACHELIB_H_
+#define L2CACHELIB_H_
+
+#define L2X0_CACHEID 0x000
+#define L2X0_CTRL 0x100
+#define L2X0_AUXCTRL 0x104
+#define L230_TAG_LATENCY 0x108
+#define L230_DATA_LATENCY 0x10C
+#define L2X0_INTCLEAR 0x220
+#define L2X0_CACHE_SYNC 0x730
+#define L2X0_INVWAY 0x77C
+#define L2X0_CLEAN_WAY 0x7BC
+#define L2X0_PFCTRL 0xF60
+#define L2X0_PWRCTRL 0xF80
+
+#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
+#define L2X0_CACHEID_PARTNUM_PL310 0x03
+
+#define L2X0_CTRL_ENABLED 0x1
+#define L2X0_CTRL_DISABLED 0x0
+
+#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)
+#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)
+#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)
+#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)
+#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)
+#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)
+#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)
+#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)
+#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)
+#define L2X0_AUXCTRL_EM (1 << 20)
+#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)
+#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)
+#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)
+#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)
+#define L2X0_AUXCTRL_SBO (1 << 25)
+#define L2X0_AUXCTRL_NSAC (1 << 27)
+#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
+#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
+#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)
+
+#define L2x0_LATENCY_1_CYCLE 0
+#define L2x0_LATENCY_2_CYCLES 1
+#define L2x0_LATENCY_3_CYCLES 2
+#define L2x0_LATENCY_4_CYCLES 3
+#define L2x0_LATENCY_5_CYCLES 4
+#define L2x0_LATENCY_6_CYCLES 5
+#define L2x0_LATENCY_7_CYCLES 6
+#define L2x0_LATENCY_8_CYCLES 7
+
+#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))
+#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
+#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
+
+VOID
+L2x0CacheInit (
+ IN UINTN L2x0Base,
+ IN UINT32 L2x0TagLatencies,
+ IN UINT32 L2x0DataLatencies,
+ IN UINT32 L2x0AuxValue,
+ IN UINT32 L2x0AuxMask,
+ IN BOOLEAN CacheEnabled
+ );
+
+#endif /* L2CACHELIB_H_ */
diff --git a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h new file mode 100644 index 0000000000..461ec16cc2 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h @@ -0,0 +1,346 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef _PL341DMC_H_ +#define _PL341DMC_H_ + + +typedef struct { + UINTN base; // base address for the controller + UINTN phy_ctrl_base; // DDR2 Phy control base + UINTN HasQos; // has QoS registers + UINTN MaxChip; // number of memory chips accessible + BOOLEAN IsUserCfg; + UINT32 User0Cfg; + UINT32 User2Cfg; + UINT32 refresh_prd; + UINT32 cas_latency; + UINT32 write_latency; + UINT32 t_mrd; + UINT32 t_ras; + UINT32 t_rc; + UINT32 t_rcd; + UINT32 t_rfc; + UINT32 t_rp; + UINT32 t_rrd; + UINT32 t_wr; + UINT32 t_wtr; + UINT32 t_xp; + UINT32 t_xsr; + UINT32 t_esr; + UINT32 MemoryCfg; + UINT32 MemoryCfg2; + UINT32 MemoryCfg3; + UINT32 ChipCfg0; + UINT32 ChipCfg1; + UINT32 ChipCfg2; + UINT32 ChipCfg3; + UINT32 t_faw; + UINT32 t_data_en; + UINT32 t_wdata_en; + UINT32 ModeReg; + UINT32 ExtModeReg; +} PL341_DMC_CONFIG; + +/* Memory config bit fields */ +#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9 0x1 +#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10 0x2 +#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11 0x3 +#define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12 0x4 +#define DMC_MEMORY_CONFIG_ROW_ADDRESS_11 (0x0 << 3) +#define DMC_MEMORY_CONFIG_ROW_ADDRESS_12 (0x1 << 3) +#define DMC_MEMORY_CONFIG_ROW_ADDRESS_13 (0x2 << 3) +#define DMC_MEMORY_CONFIG_ROW_ADDRESS_14 (0x3 << 3) +#define DMC_MEMORY_CONFIG_ROW_ADDRESS_15 (0x4 << 3) +#define DMC_MEMORY_CONFIG_ROW_ADDRESS_16 (0x5 << 3) +#define DMC_MEMORY_CONFIG_BURST_2 (0x1 << 15) +#define DMC_MEMORY_CONFIG_BURST_4 (0x2 << 15) +#define DMC_MEMORY_CONFIG_BURST_8 (0x3 << 15) +#define DMC_MEMORY_CONFIG_BURST_16 (0x4 << 15) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 (0x0 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2 (0x1 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3 (0x2 << 21) +#define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4 (0x3 << 21) + +#define DMC_MEMORY_CFG2_CLK_ASYNC (0x0 << 0) +#define DMC_MEMORY_CFG2_CLK_SYNC (0x1 << 0) +#define DMC_MEMORY_CFG2_DQM_INIT (0x1 << 2) +#define DMC_MEMORY_CFG2_CKE_INIT (0x1 << 3) +#define DMC_MEMORY_CFG2_BANK_BITS_2 (0x0 << 4) +#define DMC_MEMORY_CFG2_BANK_BITS_3 (0x3 << 4) +#define DMC_MEMORY_CFG2_MEM_WIDTH_16 (0x0 << 6) +#define DMC_MEMORY_CFG2_MEM_WIDTH_32 (0x1 << 6) +#define DMC_MEMORY_CFG2_MEM_WIDTH_64 (0x2 << 6) +#define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED (0x3 << 6) + +// +// DMC Configuration Register Map +// +#define DMC_STATUS_REG 0x00 +#define DMC_COMMAND_REG 0x04 +#define DMC_DIRECT_CMD_REG 0x08 +#define DMC_MEMORY_CONFIG_REG 0x0C +#define DMC_REFRESH_PRD_REG 0x10 +#define DMC_CAS_LATENCY_REG 0x14 +#define DMC_WRITE_LATENCY_REG 0x18 +#define DMC_T_MRD_REG 0x1C +#define DMC_T_RAS_REG 0x20 +#define DMC_T_RC_REG 0x24 +#define DMC_T_RCD_REG 0x28 +#define DMC_T_RFC_REG 0x2C +#define DMC_T_RP_REG 0x30 +#define DMC_T_RRD_REG 0x34 +#define DMC_T_WR_REG 0x38 +#define DMC_T_WTR_REG 0x3C +#define DMC_T_XP_REG 0x40 +#define DMC_T_XSR_REG 0x44 +#define DMC_T_ESR_REG 0x48 +#define DMC_MEMORY_CFG2_REG 0x4C +#define DMC_MEMORY_CFG3_REG 0x50 +#define DMC_T_FAW_REG 0x54 +#define DMC_T_RDATA_EN 0x5C /* DFI read data enable register */ +#define DMC_T_WRLAT_DIFF 0x60 /* DFI write data enable register */ + +// Returns the state of the memory controller: +#define DMC_STATUS_CONFIG 0x0 +#define DMC_STATUS_READY 0x1 +#define DMC_STATUS_PAUSED 0x2 +#define DMC_STATUS_LOWPOWER 0x3 + +// Changes the state of the memory controller: +#define DMC_COMMAND_GO 0x0 +#define DMC_COMMAND_SLEEP 0x1 +#define DMC_COMMAND_WAKEUP 0x2 +#define DMC_COMMAND_PAUSE 0x3 +#define DMC_COMMAND_CONFIGURE 0x4 +#define DMC_COMMAND_ACTIVEPAUSE 0x7 + +// Determines the command required +#define DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL 0x0 +#define DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH (0x1 << 18) +#define DMC_DIRECT_CMD_MEMCMD_MODEREG (0x2 << 18) +#define DMC_DIRECT_CMD_MEMCMD_EXTMODEREG (0x2 << 18) +#define DMC_DIRECT_CMD_MEMCMD_NOP (0x3 << 18) +#define DMC_DIRECT_CMD_MEMCMD_DPD (0x1 << 22) +#define DMC_DIRECT_CMD_BANKADDR(n) ((n & 0x3) << 16) +#define DMC_DIRECT_CMD_CHIP_ADDR(n) ((n & 0x3) << 20) + + +// +// AXI ID configuration register map +// +#define DMC_ID_0_CFG_REG 0x100 +#define DMC_ID_1_CFG_REG 0x104 +#define DMC_ID_2_CFG_REG 0x108 +#define DMC_ID_3_CFG_REG 0x10C +#define DMC_ID_4_CFG_REG 0x110 +#define DMC_ID_5_CFG_REG 0x114 +#define DMC_ID_6_CFG_REG 0x118 +#define DMC_ID_7_CFG_REG 0x11C +#define DMC_ID_8_CFG_REG 0x120 +#define DMC_ID_9_CFG_REG 0x124 +#define DMC_ID_10_CFG_REG 0x128 +#define DMC_ID_11_CFG_REG 0x12C +#define DMC_ID_12_CFG_REG 0x130 +#define DMC_ID_13_CFG_REG 0x134 +#define DMC_ID_14_CFG_REG 0x138 +#define DMC_ID_15_CFG_REG 0x13C + +// Set the QoS +#define DMC_ID_CFG_QOS_DISABLE 0 +#define DMC_ID_CFG_QOS_ENABLE 1 +#define DMC_ID_CFG_QOS_MIN 2 + + +// +// Chip configuration register map +// +#define DMC_CHIP_0_CFG_REG 0x200 +#define DMC_CHIP_1_CFG_REG 0x204 +#define DMC_CHIP_2_CFG_REG 0x208 +#define DMC_CHIP_3_CFG_REG 0x20C + +// +// User Defined Pins +// +#define DMC_USER_STATUS_REG 0x300 +#define DMC_USER_0_CFG_REG 0x304 +#define DMC_USER_1_CFG_REG 0x308 +#define DMC_FEATURE_CRTL_REG 0x30C +#define DMC_USER_2_CFG_REG 0x310 + + +// +// PHY Register Settings +// +#define PHY_PTM_DFI_CLK_RANGE 0xE00 // DDR2 PHY PTM register offset +#define PHY_PTM_IOTERM 0xE04 +#define PHY_PTM_PLL_EN 0xe0c +#define PHY_PTM_PLL_RANGE 0xe18 +#define PHY_PTM_FEEBACK_DIV 0xe1c +#define PHY_PTM_RCLK_DIV 0xe20 +#define PHY_PTM_LOCK_STATUS 0xe28 +#define PHY_PTM_INIT_DONE 0xe34 +#define PHY_PTM_ADDCOM_IOSTR_OFF 0xec8 +#define PHY_PTM_SQU_TRAINING 0xee8 +#define PHY_PTM_SQU_STAT 0xeec + +// ============================================================================== +// PIPD 40G DDR2/DDR3 PHY Register definitions +// +// Offsets from APB Base Address +// ============================================================================== +#define PHY_BYTE0_OFFSET 0x000 +#define PHY_BYTE1_OFFSET 0x200 +#define PHY_BYTE2_OFFSET 0x400 +#define PHY_BYTE3_OFFSET 0x600 + +#define PHY_BYTE0_COARSE_SQADJ_INIT 0x064 ;// Coarse squelch adjust +#define PHY_BYTE1_COARSE_SQADJ_INIT 0x264 ;// Coarse squelch adjust +#define PHY_BYTE2_COARSE_SQADJ_INIT 0x464 ;// Coarse squelch adjust +#define PHY_BYTE3_COARSE_SQADJ_INIT 0x664 ;// Coarse squelch adjust + +#define PHY_BYTE0_IOSTR_OFFSET 0x004 +#define PHY_BYTE1_IOSTR_OFFSET 0x204 +#define PHY_BYTE2_IOSTR_OFFSET 0x404 +#define PHY_BYTE3_IOSTR_OFFSET 0x604 + + +;//-------------------------------------------------------------------------- + +// DFI Clock ranges: + +#define PHY_PTM_DFI_CLK_RANGE_200MHz 0x0 +#define PHY_PTM_DFI_CLK_RANGE_201_267MHz 0x1 +#define PHY_PTM_DFI_CLK_RANGE_268_333MHz 0x2 +#define PHY_PTM_DFI_CLK_RANGE_334_400MHz 0x3 +#define PHY_PTM_DFI_CLK_RANGE_401_533MHz 0x4 +#define PHY_PTM_DFI_CLK_RANGE_534_667MHz 0x5 +#define PHY_PTM_DFI_CLK_RANGE_668_800MHz 0x6 + + + +#define PHY_PTM_DFI_CLK_RANGE_VAL PHY_PTM_DFI_CLK_RANGE_334_400MHz + +//-------------------------------------------------------------------------- + + +// PLL Range + +#define PHY_PTM_PLL_RANGE_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz +#define PHY_PTM_PLL_RANGE_400_800MHz 0x1 // b1 = frequency >= 400 MHz. +#define PHY_PTM_FEEBACK_DIV_200_400MHz 0x0 // b0 = frequency >= 200 MHz and < 400 MHz +#define PHY_PTM_FEEBACK_DIV_400_800MHz 0x1 // b1 = frequency >= 400 MHz. +#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0 +#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1 + + +// PHY Reset in SCC + +#define SCC_PHY_RST_REG_OFF 0xA0 +#define SCC_REMAP_REG_OFF 0x00 +#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset +#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset +#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset +#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset + +#define TC_UIOLHNC_MASK 0x000003C0 +#define TC_UIOLHNC_SHIFT 0x6 +#define TC_UIOLHPC_MASK 0x0000003F +#define TC_UIOLHPC_SHIFT 0x2 +#define TC_UIOHOCT_MASK 0x2 +#define TC_UIOHOCT_SHIFT 0x1 +#define TC_UIOHSTOP_SHIFT 0x0 +#define TC_UIOLHXC_VALUE 0x4 + +#define PHY_PTM_SQU_TRAINING_ENABLE 0x1 +#define PHY_PTM_SQU_TRAINING_DISABLE 0x0 + + +//-------------------------------------- +// JEDEC DDR2 Device Register definitions and settings +//-------------------------------------- +#define DDR_MODESET_SHFT 14 +#define DDR_MODESET_MR 0x0 ;// Mode register +#define DDR_MODESET_EMR 0x1 ;// Extended Mode register +#define DDR_MODESET_EMR2 0x2 +#define DDR_MODESET_EMR3 0x3 + +// +// Extended Mode Register settings +// +#define DDR_EMR_OCD_MASK 0x0000380 +#define DDR_EMR_OCD_SHIFT 0x7 +#define DDR_EMR_RTT_MASK 0x00000044 // DDR2 Device RTT (ODT) settings +#define DDR_EMR_RTT_SHIFT 0x2 +#define DDR_EMR_ODS_MASK 0x00000002 // DDR2 Output Drive Strength +#define DDR_EMR_ODS_SHIFT 0x0001 + +// Termination Values: +#define DDR_EMR_RTT_50R 0x00000044 // DDR2 50 Ohm termination +#define DDR_EMR_RTT_75R 0x00000004 // DDR2 75 Ohm termination +#define DDR_EMR_RTT_150 0x00000040 // DDR2 150 Ohm termination + +// Output Drive Strength Values: +#define DDR_EMR_ODS_FULL 0x0 // DDR2 Full Drive Strength +#define DDR_EMR_ODS_HALF 0x1 // DDR2 Half Drive Strength + +// OCD values +#define DDR_EMR_OCD_DEFAULT 0x7 +#define DDR_EMR_OCD_NS 0x0 + +#define DDR_EMR_ODS_VAL DDR_EMR_ODS_FULL + +#define DDR_SDRAM_START_ADDR 0x10000000 + + +// ---------------------------------------- +// PHY IOTERM values +// ---------------------------------------- +#define PHY_PTM_IOTERM_OFF 0x0 +#define PHY_PTM_IOTERM_150R 0x1 +#define PHY_PTM_IOTERM_75R 0x2 +#define PHY_PTM_IOTERM_50R 0x3 + +#define PHY_BYTE_IOSTR_60OHM 0x0 +#define PHY_BYTE_IOSTR_40OHM 0x1 +#define PHY_BYTE_IOSTR_30OHM 0x2 +#define PHY_BYTE_IOSTR_30AOHM 0x3 + +#define DDR2_MR_BURST_LENGTH_4 (2) +#define DDR2_MR_BURST_LENGTH_8 (3) +#define DDR2_MR_DLL_RESET (1 << 8) +#define DDR2_MR_CAS_LATENCY_4 (4 << 4) +#define DDR2_MR_CAS_LATENCY_5 (5 << 4) +#define DDR2_MR_CAS_LATENCY_6 (6 << 4) +#define DDR2_MR_WR_CYCLES_2 (1 << 9) +#define DDR2_MR_WR_CYCLES_3 (2 << 9) +#define DDR2_MR_WR_CYCLES_4 (3 << 9) +#define DDR2_MR_WR_CYCLES_5 (4 << 9) +#define DDR2_MR_WR_CYCLES_6 (5 << 9) + + +VOID PL341DmcInit ( + IN PL341_DMC_CONFIG *config + ); + +VOID PL341DmcPhyInit ( + IN UINTN DmcPhyBase + ); + +VOID PL341DmcTrainPHY ( + IN UINTN DmcPhyBase + ); + +#endif /* _PL341DMC_H_ */ diff --git a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h new file mode 100644 index 0000000000..0da47f9982 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h @@ -0,0 +1,57 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef PL354SMC_H_
+#define PL354SMC_H_
+
+#define PL354_SMC_DIRECT_CMD_OFFSET 0x10
+#define PL354_SMC_SET_CYCLES_OFFSET 0x14
+#define PL354_SMC_SET_OPMODE_OFFSET 0x18
+
+#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
+#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
+#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))
+
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
+#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
+#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
+#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
+#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
+#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
+#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)
+#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)
+#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
+#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
+
+
+#endif
diff --git a/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h b/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h index 10600a1553..60c02be139 100644 --- a/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h +++ b/ArmPlatformPkg/Include/Drivers/SP805Watchdog.h @@ -16,27 +16,24 @@ #ifndef __SP805_WATCHDOG_H__
#define __SP805_WATCHDOG_H__
-#include <Base.h>
-#include <ArmPlatform.h>
-
// SP805 Watchdog Registers
-#define SP805_WDOG_LOAD_REG (SP805_WDOG_BASE + 0x000)
-#define SP805_WDOG_CURRENT_REG (SP805_WDOG_BASE + 0x004)
-#define SP805_WDOG_CONTROL_REG (SP805_WDOG_BASE + 0x008)
-#define SP805_WDOG_INT_CLR_REG (SP805_WDOG_BASE + 0x00C)
-#define SP805_WDOG_RAW_INT_STS_REG (SP805_WDOG_BASE + 0x010)
-#define SP805_WDOG_MSK_INT_STS_REG (SP805_WDOG_BASE + 0x014)
-#define SP805_WDOG_LOCK_REG (SP805_WDOG_BASE + 0xC00)
-
-#define SP805_WDOG_PERIPH_ID0 (SP805_WDOG_BASE + 0xFE0)
-#define SP805_WDOG_PERIPH_ID1 (SP805_WDOG_BASE + 0xFE4)
-#define SP805_WDOG_PERIPH_ID2 (SP805_WDOG_BASE + 0xFE8)
-#define SP805_WDOG_PERIPH_ID3 (SP805_WDOG_BASE + 0xFEC)
-
-#define SP805_WDOG_PCELL_ID0 (SP805_WDOG_BASE + 0xFF0)
-#define SP805_WDOG_PCELL_ID1 (SP805_WDOG_BASE + 0xFF4)
-#define SP805_WDOG_PCELL_ID2 (SP805_WDOG_BASE + 0xFF8)
-#define SP805_WDOG_PCELL_ID3 (SP805_WDOG_BASE + 0xFFC)
+#define SP805_WDOG_LOAD_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x000)
+#define SP805_WDOG_CURRENT_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x004)
+#define SP805_WDOG_CONTROL_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x008)
+#define SP805_WDOG_INT_CLR_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x00C)
+#define SP805_WDOG_RAW_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x010)
+#define SP805_WDOG_MSK_INT_STS_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0x014)
+#define SP805_WDOG_LOCK_REG ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xC00)
+
+#define SP805_WDOG_PERIPH_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE0)
+#define SP805_WDOG_PERIPH_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE4)
+#define SP805_WDOG_PERIPH_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFE8)
+#define SP805_WDOG_PERIPH_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFEC)
+
+#define SP805_WDOG_PCELL_ID0 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF0)
+#define SP805_WDOG_PCELL_ID1 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF4)
+#define SP805_WDOG_PCELL_ID2 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFF8)
+#define SP805_WDOG_PCELL_ID3 ((UINT32)PcdGet32 (PcdSP805WatchdogBase) + 0xFFC)
// Timer control register bit definitions
#define SP805_WDOG_CTRL_INTEN BIT0
diff --git a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h index 26e79923d3..ba0f8520b7 100644 --- a/ArmPlatformPkg/Include/Library/ArmPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/ArmPlatformLib.h @@ -27,7 +27,6 @@ #include <Guid/MemoryTypeInformation.h> #include <Library/ArmLib.h> -#include <ArmPlatform.h> /** This structure is used by ArmVExpressGetEfiMemoryMap to describes a region of the EFI memory map @@ -98,7 +97,7 @@ ArmPlatformSecInitialize ( /** Initialize controllers that must setup in the normal world - This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei in the PEI phase. **/ diff --git a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c index 842bbe005b..b8b06f1ea7 100644 --- a/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c +++ b/ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.c @@ -22,7 +22,6 @@ #include <Drivers/PL011Uart.h> -#include <ArmPlatform.h> /* diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c index 9bccd2f14f..03361cd73a 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -15,7 +15,6 @@ **/
-#include <Base.h>
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/BaseLib.h>
@@ -24,14 +23,16 @@ #include <Library/IoLib.h>
#include <Library/RealTimeClockLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
#include <Library/ArmPlatformSysConfigLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Protocol/RealTimeClock.h>
#include <Guid/GlobalVariable.h>
-#include <ArmPlatform.h>
#include <Drivers/PL031RealTimeClock.h>
+#include <ArmPlatform.h>
+
CHAR16 mTimeZoneVariableName[] = L"PL031_TimeZone";
CHAR16 mDaylightVariableName[] = L"PL031_Daylight";
BOOLEAN mPL031Initialized = FALSE;
@@ -44,19 +45,19 @@ IdentifyPL031 ( EFI_STATUS Status;
// Check if this is a PrimeCell Peripheral
- if( ( MmioRead8( PL031_RTC_PCELL_ID0 ) != 0x0D )
- || ( MmioRead8( PL031_RTC_PCELL_ID1 ) != 0xF0 )
- || ( MmioRead8( PL031_RTC_PCELL_ID2 ) != 0x05 )
- || ( MmioRead8( PL031_RTC_PCELL_ID3 ) != 0xB1 ) ) {
+ if ( (MmioRead8 (PL031_RTC_PCELL_ID0) != 0x0D)
+ || (MmioRead8 (PL031_RTC_PCELL_ID1) != 0xF0)
+ || (MmioRead8 (PL031_RTC_PCELL_ID2) != 0x05)
+ || (MmioRead8 (PL031_RTC_PCELL_ID3) != 0xB1)) {
Status = EFI_NOT_FOUND;
goto EXIT;
}
// Check if this PrimeCell Peripheral is the SP805 Watchdog Timer
- if( ( MmioRead8( PL031_RTC_PERIPH_ID0 ) != 0x31 )
- || ( MmioRead8( PL031_RTC_PERIPH_ID1 ) != 0x10 )
- || (( MmioRead8( PL031_RTC_PERIPH_ID2 ) & 0xF) != 0x04 )
- || ( MmioRead8( PL031_RTC_PERIPH_ID3 ) != 0x00 ) ) {
+ if ( (MmioRead8 (PL031_RTC_PERIPH_ID0) != 0x31)
+ || (MmioRead8 (PL031_RTC_PERIPH_ID1) != 0x10)
+ || ((MmioRead8 (PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
+ || (MmioRead8 (PL031_RTC_PERIPH_ID3) != 0x00)) {
Status = EFI_NOT_FOUND;
goto EXIT;
}
@@ -81,18 +82,18 @@ InitializePL031 ( }
// Ensure interrupts are masked. We do not want RTC interrupts in UEFI
- if ( (MmioRead32( PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER ) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK ) {
- MmioOr32( PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
+ if ((MmioRead32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) {
+ MmioOr32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
}
// Clear any existing interrupts
- if ( (MmioRead32( PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER ) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED ) {
- MmioOr32( PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);
+ if ((MmioRead32 (PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED) {
+ MmioOr32 (PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);
}
// Start the clock counter
- if ( (MmioRead32( PL031_RTC_CR_CONTROL_REGISTER ) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED ) {
- MmioOr32( PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);
+ if ((MmioRead32 (PL031_RTC_CR_CONTROL_REGISTER) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED) {
+ MmioOr32 (PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);
}
mPL031Initialized = TRUE;
@@ -127,7 +128,7 @@ EpochToEfiTime ( UINTN ss;
UINTN J;
- if( Time->Daylight == TRUE) {
+ if (Time->Daylight == TRUE) {
}
@@ -183,7 +184,7 @@ EfiTimeToEpoch ( JulianDate = Time->Day + ((153*m + 2)/5) + (365*y) + (y/4) - (y/100) + (y/400) - 32045;
- ASSERT( JulianDate > EPOCH_JULIAN_DATE );
+ ASSERT(JulianDate > EPOCH_JULIAN_DATE);
EpochDays = JulianDate - EPOCH_JULIAN_DATE;
EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
@@ -221,7 +222,7 @@ DayValid ( if (Time->Day < 1 ||
Time->Day > DayOfMonth[Time->Month - 1] ||
(Time->Month == 2 && (!IsLeapYear (Time) && Time->Day > 28))
- ) {
+ ) {
return FALSE;
}
@@ -254,8 +255,8 @@ LibGetTime ( UINTN *Daylight = 0;
// Initialize the hardware if not already done
- if( !mPL031Initialized ) {
- Status = InitializePL031();
+ if (!mPL031Initialized) {
+ Status = InitializePL031 ();
if (EFI_ERROR (Status)) {
goto EXIT;
}
@@ -267,7 +268,7 @@ LibGetTime ( Status = ArmPlatformSysConfigGet (SYS_CFG_RTC, &EpochSeconds);
if (Status == EFI_UNSUPPORTED) {
// Battery backed up hardware RTC does not exist, revert to PL031
- EpochSeconds = MmioRead32( PL031_RTC_DR_DATA_REGISTER );
+ EpochSeconds = MmioRead32 (PL031_RTC_DR_DATA_REGISTER);
Status = EFI_SUCCESS;
} else if (EFI_ERROR (Status)) {
// Battery backed up hardware RTC exists but could not be read due to error. Abort.
@@ -275,11 +276,11 @@ LibGetTime ( } else {
// Battery backed up hardware RTC exists and we read the time correctly from it.
// Now sync the PL031 to the new time.
- MmioWrite32( PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
+ MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
}
// Ensure Time is a valid pointer
- if( Time == NULL ) {
+ if (Time == NULL) {
Status = EFI_INVALID_PARAMETER;
goto EXIT;
}
@@ -287,7 +288,7 @@ LibGetTime ( // Get the current time zone information from non-volatile storage
TimeZone = (INT16 *)GetVariable(mTimeZoneVariableName, &gEfiGlobalVariableGuid);
- if( TimeZone == NULL ) {
+ if (TimeZone == NULL) {
// The time zone variable does not exist in non-volatile storage, so create it.
Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
// Store it
@@ -297,7 +298,7 @@ LibGetTime ( EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof(Time->TimeZone),
&(Time->TimeZone)
- );
+ );
if (EFI_ERROR (Status)) {
DEBUG((EFI_D_ERROR,"LibGetTime: ERROR: TimeZone\n"));
goto EXIT;
@@ -308,13 +309,13 @@ LibGetTime ( FreePool(TimeZone);
// Check TimeZone bounds: -1440 to 1440 or 2047
- if( (( Time->TimeZone < -1440 ) || ( Time->TimeZone > 1440 ))
- && ( Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) ) {
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))
+ && (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) {
Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
}
// Adjust for the correct time zone
- if( Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE ) {
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
EpochSeconds += Time->TimeZone * SEC_PER_MIN;
}
}
@@ -322,7 +323,7 @@ LibGetTime ( // Get the current daylight information from non-volatile storage
Daylight = (UINTN *)GetVariable(mDaylightVariableName, &gEfiGlobalVariableGuid);
- if( Daylight == NULL ) {
+ if (Daylight == NULL) {
// The daylight variable does not exist in non-volatile storage, so create it.
Time->Daylight = 0;
// Store it
@@ -332,7 +333,7 @@ LibGetTime ( EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof(Time->Daylight),
&(Time->Daylight)
- );
+ );
if (EFI_ERROR (Status)) {
DEBUG((EFI_D_ERROR,"LibGetTime: ERROR: Daylight\n"));
goto EXIT;
@@ -343,20 +344,23 @@ LibGetTime ( FreePool(Daylight);
// Adjust for the correct period
- if( (Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT ) {
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
// Convert to adjusted time, i.e. spring forwards one hour
EpochSeconds += SEC_PER_HOUR;
}
}
// Convert from internal 32-bit time to UEFI time
- EpochToEfiTime( EpochSeconds, Time );
+ EpochToEfiTime (EpochSeconds, Time);
// Update the Capabilities info
- if( Capabilities != NULL ) {
- Capabilities->Resolution = PL031_COUNTS_PER_SECOND; /* PL031 runs at frequency 1Hz */
- Capabilities->Accuracy = PL031_PPM_ACCURACY; /* Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000 */
- Capabilities->SetsToZero = FALSE; /* FALSE: Setting the time does not clear the values below the resolution level */
+ if (Capabilities != NULL) {
+ // PL031 runs at frequency 1Hz
+ Capabilities->Resolution = PL031_COUNTS_PER_SECOND;
+ // Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000
+ Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy);
+ // FALSE: Setting the time does not clear the values below the resolution level
+ Capabilities->SetsToZero = FALSE;
}
EXIT:
@@ -391,41 +395,41 @@ LibSetTime ( // to the range 1998 .. 2011
// Check the input parameters' range.
- if ( ( Time->Year < 1998 ) ||
- ( Time->Year > 2099 ) ||
- ( Time->Month < 1 ) ||
- ( Time->Month > 12 ) ||
- (!DayValid (Time) ) ||
- ( Time->Hour > 23 ) ||
- ( Time->Minute > 59 ) ||
- ( Time->Second > 59 ) ||
- ( Time->Nanosecond > 999999999 ) ||
- ( !((Time->TimeZone == EFI_UNSPECIFIED_TIMEZONE) || ((Time->TimeZone >= -1440) && (Time->TimeZone <= 1440))) ) ||
- ( Time->Daylight & (~(EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT)) )
- ) {
+ if ((Time->Year < 1998) ||
+ (Time->Year > 2099) ||
+ (Time->Month < 1 ) ||
+ (Time->Month > 12 ) ||
+ (!DayValid (Time) ) ||
+ (Time->Hour > 23 ) ||
+ (Time->Minute > 59 ) ||
+ (Time->Second > 59 ) ||
+ (Time->Nanosecond > 999999999) ||
+ (!((Time->TimeZone == EFI_UNSPECIFIED_TIMEZONE) || ((Time->TimeZone >= -1440) && (Time->TimeZone <= 1440)))) ||
+ (Time->Daylight & (~(EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT)))
+ ) {
Status = EFI_INVALID_PARAMETER;
goto EXIT;
}
// Initialize the hardware if not already done
- if( !mPL031Initialized ) {
- Status = InitializePL031();
+ if (!mPL031Initialized) {
+ Status = InitializePL031 ();
if (EFI_ERROR (Status)) {
goto EXIT;
}
}
- EpochSeconds = EfiTimeToEpoch( Time );
+ EpochSeconds = EfiTimeToEpoch (Time);
// Adjust for the correct time zone, i.e. convert to UTC time zone
- if( Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE ) {
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
EpochSeconds -= Time->TimeZone * SEC_PER_MIN;
}
// TODO: Automatic Daylight activation
// Adjust for the correct period
- if( (Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT ) {
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
// Convert to un-adjusted time, i.e. fall back one hour
EpochSeconds -= SEC_PER_HOUR;
}
@@ -445,7 +449,7 @@ LibSetTime ( // Set the PL031
- MmioWrite32( PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
+ MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
// The accesses to Variable Services can be very slow, because we may be writing to Flash.
// Do this after having set the RTC.
@@ -457,7 +461,7 @@ LibSetTime ( EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof(Time->TimeZone),
&(Time->TimeZone)
- );
+ );
if (EFI_ERROR (Status)) {
DEBUG((EFI_D_ERROR,"LibSetTime: ERROR: TimeZone\n"));
goto EXIT;
@@ -470,7 +474,7 @@ LibSetTime ( EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof(Time->Daylight),
&(Time->Daylight)
- );
+ );
if (EFI_ERROR (Status)) {
DEBUG((EFI_D_ERROR,"LibSetTime: ERROR: Daylight\n"));
goto EXIT;
@@ -564,7 +568,7 @@ LibRtcInitialize ( &Handle,
&gEfiRealTimeClockArchProtocolGuid, NULL,
NULL
- );
+ );
return Status;
}
diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf index 8a249ec889..24c74d2d11 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf @@ -35,4 +35,9 @@ IoLib
UefiLib
DebugLib
+ PcdLib
ArmPlatformSysConfigLib
+
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy
diff --git a/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c b/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c index 2508897391..6dc79f8e5a 100644 --- a/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c +++ b/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.c @@ -20,7 +20,9 @@ #include <Library/PcdLib.h> #include <Library/IoLib.h> #include <Drivers/SP804Timer.h> -#include <ArmPlatform.h> + +#define SP804_TIMER_METRONOME_BASE (UINTN)PcdGet32 (PcdSP804TimerPerformanceBase) +#define SP804_TIMER_PERFORMANCE_BASE (UINTN)PcdGet32 (PcdSP804TimerMetronomeBase) // Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter // Note: ArmVE's Timer0 and Timer1 are used by TimerDxe. @@ -31,28 +33,28 @@ TimerConstructor ( ) { // Check if Timer 2 is already initialized - if (MmioRead32(SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { + if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { return RETURN_SUCCESS; } else { // Configure timer 2 for one shot operation, 32 bits, no prescaler, and interrupt disabled - MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); + MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ONESHOT | SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); // Preload the timer count register - MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, 1); + MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_LOAD_REG, 1); // Enable the timer - MmioOr32 (SP804_TIMER2_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); + MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); } // Check if Timer 3 is already initialized - if (MmioRead32(SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { + if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { return RETURN_SUCCESS; } else { // Configure timer 3 for free running operation, 32 bits, no prescaler, interrupt disabled - MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); + MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); // Enable the timer - MmioOr32 (SP804_TIMER3_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); + MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); } return RETURN_SUCCESS; @@ -77,11 +79,11 @@ MicroSecondDelay ( UINTN Index; // Reload the counter for each 1Mhz to avoid an overflow in the load value - for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804FrequencyInMHz); Index++) { + for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804TimerFrequencyInMHz); Index++) { // load the timer count register - MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, MicroSeconds); + MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_LOAD_REG, MicroSeconds); - while (MmioRead32 (SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) { + while (MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG) > 0) { ; } } @@ -113,11 +115,11 @@ NanoSecondDelay ( MicroSeconds += ((UINT32)NanoSeconds % 1000) == 0 ? 0 : 1; // Reload the counter for each 1Mhz to avoid an overflow in the load value - for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804FrequencyInMHz); Index++) { + for (Index = 0; Index < (UINTN)PcdGet32(PcdSP804TimerFrequencyInMHz); Index++) { // load the timer count register - MmioWrite32 (SP804_TIMER2_BASE + SP804_TIMER_LOAD_REG, MicroSeconds); + MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_LOAD_REG, MicroSeconds); - while (MmioRead32 (SP804_TIMER2_BASE + SP804_TIMER_CURRENT_REG) > 0) { + while (MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG) > 0) { ; } } @@ -145,7 +147,7 @@ GetPerformanceCounter ( // Free running 64-bit/32-bit counter is needed here. // Don't think we need this to boot, just to do performance profile UINT64 Value; - Value = MmioRead32 (SP804_TIMER3_BASE + SP804_TIMER_CURRENT_REG); + Value = MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CURRENT_REG); ASSERT(Value > 0); return Value; } diff --git a/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf b/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf index 1cbb32ecb6..0928cae53b 100644 --- a/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf +++ b/ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf @@ -38,5 +38,7 @@ BaseLib [Pcd] - gArmPlatformTokenSpaceGuid.PcdSP804FrequencyInMHz + gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz diff --git a/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c b/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c index d745357164..f4c27c5750 100755 --- a/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c +++ b/ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.c @@ -95,12 +95,8 @@ InitializeMemory ( )
{
EFI_STATUS Status;
- EFI_RESOURCE_ATTRIBUTE_TYPE Attributes;
- ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR* EfiMemoryMap;
- UINTN Index;
UINTN SystemMemoryTop;
UINTN UefiMemoryBase;
- UINTN UefiMemorySize;
DEBUG ((EFI_D_ERROR, "Memory Init PEIM Loaded\n"));
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index 19683cbca8..17a0002dee 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -12,8 +12,6 @@ *
**/
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
#include <Library/ArmMPCoreMailBoxLib.h>
#include <Chipset/ArmV7.h>
#include <Drivers/PL390Gic.h>
diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c index c09494557b..4d8331219a 100644 --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c @@ -12,8 +12,6 @@ *
**/
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
#include <Chipset/ArmV7.h>
#include "PrePeiCore.h"
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 56186471fa..ccf0e7d3d4 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -13,8 +13,6 @@ *
**/
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h index 0f8778c154..7a369b4f6f 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h @@ -15,6 +15,9 @@ #ifndef __PREPEICORE_H_
#define __PREPEICORE_H_
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
#include <PiPei.h>
#include <Ppi/TemporaryRamSupport.h>
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf index 52e6d959c7..b696190acc 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -59,3 +59,6 @@ gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmTokenSpaceGuid.PcdNormalFvBaseAddress
+ gArmTokenSpaceGuid.PcdNormalFvSize
diff --git a/ArmPlatformPkg/PrePi/Exception.S b/ArmPlatformPkg/PrePi/Exception.S index 628793e031..b07f0e8d00 100755 --- a/ArmPlatformPkg/PrePi/Exception.S +++ b/ArmPlatformPkg/PrePi/Exception.S @@ -29,7 +29,6 @@ GCC_ASM_EXPORT(PrePiVectorTable) //Default Exception Handlers //============================================================ - ASM_PFX(PrePiVectorTable): b _DefaultResetHandler b _DefaultUndefined |