diff options
author | Ryan Harkin <ryan.harkin@linaro.org> | 2016-02-03 11:38:12 +0000 |
---|---|---|
committer | Leif Lindholm <leif.lindholm@linaro.org> | 2016-02-09 13:33:10 +0000 |
commit | 9a8f6fb40712938ad562e9a9095dc06dff9c1fce (patch) | |
tree | 777f09e66fb3a54910f98cead4393d0374f0d235 /ArmPlatformPkg | |
parent | bfc7793bd2df67810e0fb09ae76f587659a04946 (diff) | |
download | edk2-platforms-9a8f6fb40712938ad562e9a9095dc06dff9c1fce.tar.xz |
ArmPlatformPkg: remove unused Sec library
The Sec library was built by the AARCH64 FVP models, but the binary was
unused because it was part of a legacy booting strategy from before ARM
Trusted Firmware came along.
This change requires changes in OpenPlatformPkg to remove the Sec binary
from the FVP build.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Diffstat (limited to 'ArmPlatformPkg')
-rw-r--r-- | ArmPlatformPkg/Sec/AArch64/Arch.c | 25 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/AArch64/Helper.S | 93 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/AArch64/SecEntryPoint.S | 139 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Arm/Arch.c | 25 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Arm/Helper.S | 75 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Arm/Helper.asm | 77 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Arm/SecEntryPoint.S | 118 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm | 122 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Sec.c | 200 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/Sec.inf | 85 | ||||
-rw-r--r-- | ArmPlatformPkg/Sec/SecInternal.h | 83 |
11 files changed, 0 insertions, 1042 deletions
diff --git a/ArmPlatformPkg/Sec/AArch64/Arch.c b/ArmPlatformPkg/Sec/AArch64/Arch.c deleted file mode 100644 index 6e7d58e5d4..0000000000 --- a/ArmPlatformPkg/Sec/AArch64/Arch.c +++ /dev/null @@ -1,25 +0,0 @@ -/** @file
-*
-* Copyright (c) 2013, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Chipset/AArch64.h>
-
-VOID
-EFIAPI
-ArmSecArchTrustzoneInit (
- VOID
- )
-{
- // Do not trap any access to Floating Point and Advanced SIMD in EL3.
- ArmWriteCptr (0);
-}
diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S deleted file mode 100644 index 3b58e12292..0000000000 --- a/ArmPlatformPkg/Sec/AArch64/Helper.S +++ /dev/null @@ -1,93 +0,0 @@ -#========================================================================================
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http:#opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#=======================================================================================
-
-#include <AsmMacroIoLibV8.h>
-#include <Chipset/AArch64.h>
-
-#start of the code section
-.text
-.align 3
-
-GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
-GCC_ASM_EXPORT(enter_monitor_mode)
-GCC_ASM_EXPORT(return_from_exception)
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)
-GCC_ASM_EXPORT(set_non_secure_mode)
-
-// Switch from EL3 to NS-EL1
-ASM_PFX(SwitchToNSExceptionLevel1):
- // Now setup our EL1. Controlled by EL2 config on Model
- mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
- orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
-
- // Send all interrupts to their respective Exception levels for EL2
- and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
- msr hcr_el2, x0 // Write back our settings
-
- msr cptr_el2, xzr // Disable copro traps to EL2
-
- msr sctlr_el2, xzr
-
- // Enable architected timer access
- mrs x0, cnthctl_el2
- orr x0, x0, #3 // Enable EL1 access to timers
- msr cnthctl_el2, x0
-
- mrs x0, cntkctl_el1
- orr x0, x0, #3 // EL0 access to counters
- msr cntkctl_el1, x0
-
- // Set ID regs
- mrs x0, midr_el1
- mrs x1, mpidr_el1
- msr vpidr_el2, x0
- msr vmpidr_el2, x1
-
- ret
-
-
-// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
-// we don't need a mode switch, just setup the Arguments and jump.
-// x0: Monitor World EntryPoint
-// x1: MpId
-// x2: SecBootMode
-// x3: Secure Monitor mode stack
-ASM_PFX(enter_monitor_mode):
- mov x4, x0 // Swap EntryPoint and MpId registers
- mov x0, x1
- mov x1, x2
- mov x2, x3
- br x4
-
-// Put the address in correct ELR_ELx and do a eret.
-// We may need to do some config before we change to another Mode.
-ASM_PFX(return_from_exception):
- msr elr_el3, x0
- eret
-
-// For AArch64 we need to construct the spsr we want from individual bits and pieces.
-ASM_PFX(copy_cpsr_into_spsr):
- mrs x0, CurrentEl // Get the current exception level we are running at.
- mrs x1, SPSel // Which Stack are we using
- orr x0, x0, x1
- mrs x1, daif // Which interrupts are enabled
- orr x0, x0, x1
- msr spsr_el3, x0 // Write to spsr
- ret
-
-// Get this from platform file.
-ASM_PFX(set_non_secure_mode):
- msr spsr_el3, x0
- ret
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPlatformPkg/Sec/AArch64/SecEntryPoint.S b/ArmPlatformPkg/Sec/AArch64/SecEntryPoint.S deleted file mode 100644 index 000b56f573..0000000000 --- a/ArmPlatformPkg/Sec/AArch64/SecEntryPoint.S +++ /dev/null @@ -1,139 +0,0 @@ -//
-// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AutoGen.h>
-#include <AsmMacroIoLibV8.h>
-#include "SecInternal.h"
-
-.text
-.align 3
-
-GCC_ASM_IMPORT(CEntryPoint)
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
-GCC_ASM_IMPORT(ArmDisableInterrupts)
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
-GCC_ASM_IMPORT(ArmReadMpidr)
-GCC_ASM_IMPORT(ArmCallWFE)
-GCC_ASM_EXPORT(_ModuleEntryPoint)
-
-StartupAddr: .8byte ASM_PFX(CEntryPoint)
-
-ASM_PFX(_ModuleEntryPoint):
-
-// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
-// and configure the system accordingly. EL2 is default if possible.
-// If we started in EL3 we need to switch and run at EL2.
-// If we are running at EL2 stay in EL2
-// If we are starting at EL1 stay in EL1.
-
-// Sec only runs in EL3. Othewise we jump to PEI without changing anything.
-// If Sec runs we change to EL2 before switching to PEI.
-
-// Which EL are we running at? Every EL needs some level of setup...
- EL1_OR_EL2_OR_EL3(x0)
-1:// If we are at EL1 or EL2 leave SEC for PEI.
-2:b ASM_PFX(JumpToPEI)
- // If we are at EL3 we need to configure it and switch to EL2
-3:b ASM_PFX(MainEntryPoint)
-
-ASM_PFX(MainEntryPoint):
- // First ensure all interrupts are disabled
- bl ASM_PFX(ArmDisableInterrupts)
-
- // Ensure that the MMU and caches are off
- bl ASM_PFX(ArmDisableCachesAndMmu)
-
- // By default, we are doing a cold boot
- mov x10, #ARM_SEC_COLD_BOOT
-
- // Jump to Platform Specific Boot Action function
- bl ASM_PFX(ArmPlatformSecBootAction)
-
-_IdentifyCpu:
- // Identify CPU ID
- bl ASM_PFX(ArmReadMpidr)
- // Keep a copy of the MpId register value
- mov x5, x0
-
- // Is it the Primary Core ?
- bl ASM_PFX(ArmPlatformIsPrimaryCore)
- cmp x0, #1
- // Only the primary core initialize the memory (SMC)
- b.eq _InitMem
-
-_WaitInitMem:
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
- // Otherwise we have to wait the Primary Core to finish the initialization
- cmp x10, #ARM_SEC_COLD_BOOT
- b.ne _SetupSecondaryCoreStack
-
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
- bl ASM_PFX(ArmCallWFE)
- // Now the Init Mem is initialized, we setup the secondary core stacks
- b _SetupSecondaryCoreStack
-
-_InitMem:
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
- cmp x10, #ARM_SEC_COLD_BOOT
- b.ne _SetupPrimaryCoreStack
-
- // Initialize Init Boot Memory
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)
-
-_SetupPrimaryCoreStack:
- // Get the top of the primary stacks (and the base of the secondary stacks)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)
- add x1, x1, x2
-
- mov sp, x1
- b _PrepareArguments
-
-_SetupSecondaryCoreStack:
- // Get the top of the primary stacks (and the base of the secondary stacks)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)
- add x6, x1, x2
-
- // Get the Core Position
- mov x0, x5
- bl ASM_PFX(ArmPlatformGetCorePosition)
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
- add x0, x0, #1
-
- // StackOffset = CorePos * StackSize
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), x2)
- mul x0, x0, x2
- // SP = StackBase + StackOffset
- add sp, x6, x0
-
-_PrepareArguments:
- // Move sec startup address into a data register
- // Ensure we're jumping to FV version of the code (not boot remapped alias)
- ldr x3, StartupAddr
-
- // Jump to SEC C code
- // r0 = mp_id
- // r1 = Boot Mode
- mov x0, x5
- mov x1, x10
- blr x3
-
- ret
-
-ASM_PFX(JumpToPEI):
- LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), x0)
- blr x0
diff --git a/ArmPlatformPkg/Sec/Arm/Arch.c b/ArmPlatformPkg/Sec/Arm/Arch.c deleted file mode 100644 index 85df0816ef..0000000000 --- a/ArmPlatformPkg/Sec/Arm/Arch.c +++ /dev/null @@ -1,25 +0,0 @@ -/** @file
-*
-* Copyright (c) 2013, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Chipset/ArmV7.h>
-
-VOID
-EFIAPI
-ArmSecArchTrustzoneInit (
- VOID
- )
-{
- // Write to CP15 Non-secure Access Control Register
- ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
-}
diff --git a/ArmPlatformPkg/Sec/Arm/Helper.S b/ArmPlatformPkg/Sec/Arm/Helper.S deleted file mode 100644 index 1922321565..0000000000 --- a/ArmPlatformPkg/Sec/Arm/Helper.S +++ /dev/null @@ -1,75 +0,0 @@ -#========================================================================================
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#=======================================================================================
-
-#start of the code section
-.text
-.align 3
-
-GCC_ASM_EXPORT(return_from_exception)
-GCC_ASM_EXPORT(enter_monitor_mode)
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)
-GCC_ASM_EXPORT(set_non_secure_mode)
-
-# r0: Monitor World EntryPoint
-# r1: MpId
-# r2: SecBootMode
-# r3: Secure Monitor mode stack
-ASM_PFX(enter_monitor_mode):
- cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack
- moveq r3, sp
-
- mrs r4, cpsr @ Save current mode (SVC) in r4
- bic r5, r4, #0x1f @ Clear all mode bits
- orr r5, r5, #0x16 @ Set bits for Monitor mode
- msr cpsr_cxsf, r5 @ We are now in Monitor Mode
-
- mov sp, r3 @ Set the stack of the Monitor Mode
-
- mov lr, r0 @ Use the pass entrypoint as lr
-
- msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel
-
- mov r4, r0 @ Swap EntryPoint and MpId registers
- mov r0, r1
- mov r1, r2
- mov r2, r3
-
- bx r4
-
-# Return-from-exception is not an interworking return, so we must do it
-# in two steps, in case r0 has the Thumb bit set.
-ASM_PFX(return_from_exception):
- adr lr, returned_exception
- movs pc, lr
-returned_exception: @ We are now in non-secure state
- bx r0
-
-# Save the current Program Status Register (PSR) into the Saved PSR
-ASM_PFX(copy_cpsr_into_spsr):
- mrs r0, cpsr
- msr spsr_cxsf, r0
- bx lr
-
-# Set the Non Secure Mode
-ASM_PFX(set_non_secure_mode):
- push { r1 }
- and r0, r0, #0x1f @ Keep only the mode bits
- mrs r1, spsr @ Read the spsr
- bic r1, r1, #0x1f @ Clear all mode bits
- orr r1, r1, r0
- msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch)
- isb
- pop { r1 }
- bx lr @ return (hopefully thumb-safe!)
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPlatformPkg/Sec/Arm/Helper.asm b/ArmPlatformPkg/Sec/Arm/Helper.asm deleted file mode 100644 index 0a2baaf19e..0000000000 --- a/ArmPlatformPkg/Sec/Arm/Helper.asm +++ /dev/null @@ -1,77 +0,0 @@ -//
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
- EXPORT return_from_exception
- EXPORT enter_monitor_mode
- EXPORT copy_cpsr_into_spsr
- EXPORT set_non_secure_mode
-
- AREA Helper, CODE, READONLY
-
-// r0: Monitor World EntryPoint
-// r1: MpId
-// r2: SecBootMode
-// r3: Secure Monitor mode stack
-enter_monitor_mode FUNCTION
- cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack
- moveq r3, sp
-
- mrs r4, cpsr // Save current mode (SVC) in r4
- bic r5, r4, #0x1f // Clear all mode bits
- orr r5, r5, #0x16 // Set bits for Monitor mode
- msr cpsr_cxsf, r5 // We are now in Monitor Mode
-
- mov sp, r3 // Set the stack of the Monitor Mode
-
- mov lr, r0 // Use the pass entrypoint as lr
-
- msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel
-
- mov r4, r0 // Swap EntryPoint and MpId registers
- mov r0, r1
- mov r1, r2
- mov r2, r3
-
- bx r4
- ENDFUNC
-
-// Return-from-exception is not an interworking return, so we must do it
-// in two steps, in case r0 has the Thumb bit set.
-return_from_exception
- adr lr, returned_exception
- movs pc, lr
-returned_exception // We are now in non-secure state
- bx r0
-
-// Save the current Program Status Register (PSR) into the Saved PSR
-copy_cpsr_into_spsr
- mrs r0, cpsr
- msr spsr_cxsf, r0
- bx lr
-
-// Set the Non Secure Mode
-set_non_secure_mode
- push { r1 }
- and r0, r0, #0x1f // Keep only the mode bits
- mrs r1, spsr // Read the spsr
- bic r1, r1, #0x1f // Clear all mode bits
- orr r1, r1, r0
- msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)
- isb
- pop { r1 }
- bx lr // return (hopefully thumb-safe!)
-
-dead
- B dead
-
- END
diff --git a/ArmPlatformPkg/Sec/Arm/SecEntryPoint.S b/ArmPlatformPkg/Sec/Arm/SecEntryPoint.S deleted file mode 100644 index 73c264810e..0000000000 --- a/ArmPlatformPkg/Sec/Arm/SecEntryPoint.S +++ /dev/null @@ -1,118 +0,0 @@ -//
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AutoGen.h>
-#include <AsmMacroIoLib.h>
-#include "SecInternal.h"
-
-.text
-.align 3
-
-GCC_ASM_IMPORT(CEntryPoint)
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
-GCC_ASM_IMPORT(ArmDisableInterrupts)
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
-GCC_ASM_IMPORT(ArmReadMpidr)
-GCC_ASM_IMPORT(ArmCallWFE)
-GCC_ASM_EXPORT(_ModuleEntryPoint)
-
-StartupAddr: .word ASM_PFX(CEntryPoint)
-
-ASM_PFX(_ModuleEntryPoint):
- // First ensure all interrupts are disabled
- bl ASM_PFX(ArmDisableInterrupts)
-
- // Ensure that the MMU and caches are off
- bl ASM_PFX(ArmDisableCachesAndMmu)
-
- // By default, we are doing a cold boot
- mov r10, #ARM_SEC_COLD_BOOT
-
- // Jump to Platform Specific Boot Action function
- blx ASM_PFX(ArmPlatformSecBootAction)
-
-_IdentifyCpu:
- // Identify CPU ID
- bl ASM_PFX(ArmReadMpidr)
- // Keep a copy of the MpId register value
- mov r9, r0
-
- // Is it the Primary Core ?
- bl ASM_PFX(ArmPlatformIsPrimaryCore)
- cmp r0, #1
- // Only the primary core initialize the memory (SMC)
- beq _InitMem
-
-_WaitInitMem:
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
- // Otherwise we have to wait the Primary Core to finish the initialization
- cmp r10, #ARM_SEC_COLD_BOOT
- bne _SetupSecondaryCoreStack
-
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
- bl ASM_PFX(ArmCallWFE)
- // Now the Init Mem is initialized, we setup the secondary core stacks
- b _SetupSecondaryCoreStack
-
-_InitMem:
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
- cmp r10, #ARM_SEC_COLD_BOOT
- bne _SetupPrimaryCoreStack
-
- // Initialize Init Boot Memory
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)
-
-_SetupPrimaryCoreStack:
- // Get the top of the primary stacks (and the base of the secondary stacks)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
- add r1, r1, r2
-
- mov sp, r1
- b _PrepareArguments
-
-_SetupSecondaryCoreStack:
- // Get the top of the primary stacks (and the base of the secondary stacks)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
- add r6, r1, r2
-
- // Get the Core Position
- mov r0, r9
- bl ASM_PFX(ArmPlatformGetCorePosition)
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
- add r0, r0, #1
-
- // StackOffset = CorePos * StackSize
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
- mul r0, r0, r2
- // SP = StackBase + StackOffset
- add sp, r6, r0
-
-_PrepareArguments:
- // Move sec startup address into a data register
- // Ensure we're jumping to FV version of the code (not boot remapped alias)
- ldr r3, StartupAddr
-
- // Jump to SEC C code
- // r0 = mp_id
- // r1 = Boot Mode
- mov r0, r9
- mov r1, r10
- blx r3
-
-_NeverReturn:
- b _NeverReturn
diff --git a/ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm b/ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm deleted file mode 100644 index c0cd410699..0000000000 --- a/ArmPlatformPkg/Sec/Arm/SecEntryPoint.asm +++ /dev/null @@ -1,122 +0,0 @@ -//
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AutoGen.h>
-#include <AsmMacroIoLib.h>
-#include "SecInternal.h"
-
- INCLUDE AsmMacroIoLib.inc
-
- IMPORT CEntryPoint
- IMPORT ArmPlatformIsPrimaryCore
- IMPORT ArmPlatformGetCorePosition
- IMPORT ArmPlatformSecBootAction
- IMPORT ArmPlatformSecBootMemoryInit
- IMPORT ArmDisableInterrupts
- IMPORT ArmDisableCachesAndMmu
- IMPORT ArmReadMpidr
- IMPORT ArmCallWFE
- EXPORT _ModuleEntryPoint
-
- PRESERVE8
- AREA SecEntryPoint, CODE, READONLY
-
-StartupAddr DCD CEntryPoint
-
-_ModuleEntryPoint FUNCTION
- // First ensure all interrupts are disabled
- bl ArmDisableInterrupts
-
- // Ensure that the MMU and caches are off
- bl ArmDisableCachesAndMmu
-
- // By default, we are doing a cold boot
- mov r10, #ARM_SEC_COLD_BOOT
-
- // Jump to Platform Specific Boot Action function
- blx ArmPlatformSecBootAction
-
-_IdentifyCpu
- // Identify CPU ID
- bl ArmReadMpidr
- // Keep a copy of the MpId register value
- mov r9, r0
-
- // Is it the Primary Core ?
- bl ArmPlatformIsPrimaryCore
- cmp r0, #1
- // Only the primary core initialize the memory (SMC)
- beq _InitMem
-
-_WaitInitMem
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
- // Otherwise we have to wait the Primary Core to finish the initialization
- cmp r10, #ARM_SEC_COLD_BOOT
- bne _SetupSecondaryCoreStack
-
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
- bl ArmCallWFE
- // Now the Init Mem is initialized, we setup the secondary core stacks
- b _SetupSecondaryCoreStack
-
-_InitMem
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
- cmp r10, #ARM_SEC_COLD_BOOT
- bne _SetupPrimaryCoreStack
-
- // Initialize Init Boot Memory
- bl ArmPlatformSecBootMemoryInit
-
-_SetupPrimaryCoreStack
- // Get the top of the primary stacks (and the base of the secondary stacks)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
- add r1, r1, r2
-
- mov sp, r1
- b _PrepareArguments
-
-_SetupSecondaryCoreStack
- // Get the top of the primary stacks (and the base of the secondary stacks)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
- add r6, r1, r2
-
- // Get the Core Position
- mov r0, r9
- bl ArmPlatformGetCorePosition
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
- add r0, r0, #1
-
- // StackOffset = CorePos * StackSize
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
- mul r0, r0, r2
- // SP = StackBase + StackOffset
- add sp, r6, r0
-
-_PrepareArguments
- // Move sec startup address into a data register
- // Ensure we're jumping to FV version of the code (not boot remapped alias)
- ldr r3, StartupAddr
-
- // Jump to SEC C code
- // r0 = mp_id
- // r1 = Boot Mode
- mov r0, r9
- mov r1, r10
- blx r3
- ENDFUNC
-
-_NeverReturn
- b _NeverReturn
- END
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c deleted file mode 100644 index 7127395e61..0000000000 --- a/ArmPlatformPkg/Sec/Sec.c +++ /dev/null @@ -1,200 +0,0 @@ -/** @file
-* Main file supporting the SEC Phase on ARM Platforms
-*
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Library/ArmTrustedMonitorLib.h>
-#include <Library/DebugAgentLib.h>
-#include <Library/PrintLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/SerialPortLib.h>
-#include <Library/ArmGicLib.h>
-#include <Library/ArmPlatformLib.h>
-
-#include "SecInternal.h"
-
-#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
-
-VOID
-CEntryPoint (
- IN UINTN MpId,
- IN UINTN SecBootMode
- )
-{
- CHAR8 Buffer[100];
- UINTN CharCount;
- UINTN JumpAddress;
-
- // Invalidate the data cache. Doesn't have to do the Data cache clean.
- ArmInvalidateDataCache ();
-
- // Invalidate Instruction Cache
- ArmInvalidateInstructionCache ();
-
- // Invalidate I & D TLBs
- ArmInvalidateTlb ();
-
- // CPU specific settings
- ArmCpuSetup (MpId);
-
- // Enable Floating Point Coprocessor if supported by the platform
- if (FixedPcdGet32 (PcdVFPEnabled)) {
- ArmEnableVFP ();
- }
-
- // Initialize peripherals that must be done at the early stage
- // Example: Some L2 controller, interconnect, clock, DMC, etc
- ArmPlatformSecInitialize (MpId);
-
- // Primary CPU clears out the SCU tag RAMs, secondaries wait
- if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
- if (ArmIsMpCore()) {
- // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
- ArmCallSEV ();
- }
-
- // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
- // In non SEC modules the init call is in autogenerated code.
- SerialPortInitialize ();
-
- // Start talking
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
- } else {
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
- }
- SerialPortWrite ((UINT8 *) Buffer, CharCount);
-
- // Initialize the Debug Agent for Source Level Debugging
- InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
- SaveAndSetDebugTimerInterrupt (TRUE);
-
- // Enable the GIC distributor and CPU Interface
- // - no other Interrupts are enabled, doesn't have to worry about the priority.
- // - all the cores are in secure state, use secure SGI's
- ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
- } else {
- // Enable the GIC CPU Interface
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
- }
-
- // Enable Full Access to CoProcessors
- ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
-
- // Test if Trustzone is supported on this platform
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {
- if (ArmIsMpCore ()) {
- // Setup SMP in Non Secure world
- ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
- }
-
- // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
- // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
- ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
- ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
-
- // Enter Monitor Mode
- enter_monitor_mode (
- (UINTN)TrustedWorldInitialization, MpId, SecBootMode,
- (VOID*) (PcdGet32 (PcdCPUCoresSecMonStackBase) +
- (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))
- );
- } else {
- if (ArmPlatformIsPrimaryCore (MpId)) {
- SerialPrint ("Trust Zone Configuration is disabled\n\r");
- }
-
- // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
- // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
- // Status Register as the the current one (CPSR).
- copy_cpsr_into_spsr ();
-
- // Call the Platform specific function to execute additional actions if required
- JumpAddress = PcdGet64 (PcdFvBaseAddress);
- ArmPlatformSecExtraAction (MpId, &JumpAddress);
-
- NonTrustedWorldTransition (MpId, JumpAddress);
- }
- ASSERT (0); // We must never return from the above function
-}
-
-VOID
-TrustedWorldInitialization (
- IN UINTN MpId,
- IN UINTN SecBootMode
- )
-{
- UINTN JumpAddress;
-
- //-------------------- Monitor Mode ---------------------
-
- // Set up Monitor World (Vector Table, etc)
- ArmSecureMonitorWorldInitialize ();
-
- // Transfer the interrupt to Non-secure World
- ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
-
- // Initialize platform specific security policy
- ArmPlatformSecTrustzoneInit (MpId);
-
- // Setup the Trustzone Chipsets
- if (SecBootMode == ARM_SEC_COLD_BOOT) {
- if (ArmPlatformIsPrimaryCore (MpId)) {
- if (ArmIsMpCore()) {
- // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
- ArmCallSEV ();
- }
- } else {
- // The secondary cores need to wait until the Trustzone chipsets configuration is done
- // before switching to Non Secure World
-
- // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
- ArmCallWFE ();
- }
- }
-
- // Call the Platform specific function to execute additional actions if required
- JumpAddress = PcdGet64 (PcdFvBaseAddress);
- ArmPlatformSecExtraAction (MpId, &JumpAddress);
-
- // Initialize architecture specific security policy
- ArmSecArchTrustzoneInit ();
-
- // CP15 Secure Configuration Register
- ArmWriteScr (PcdGet32 (PcdArmScr));
-
- NonTrustedWorldTransition (MpId, JumpAddress);
-}
-
-VOID
-NonTrustedWorldTransition (
- IN UINTN MpId,
- IN UINTN JumpAddress
- )
-{
- // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
- // By not set, the mode for Non Secure World is SVC
- if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
- set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
- }
-
- return_from_exception (JumpAddress);
- //-------------------- Non Secure Mode ---------------------
-
- // PEI Core should always load and never return
- ASSERT (FALSE);
-}
-
diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf deleted file mode 100644 index 7f7243f98f..0000000000 --- a/ArmPlatformPkg/Sec/Sec.inf +++ /dev/null @@ -1,85 +0,0 @@ -#/** @file
-# SEC - Reset vector code that jumps to C and starts the PEI phase
-#
-# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#**/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = ArmPlatformSec
- FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
-
-[Sources]
- Sec.c
-
-[Sources.ARM]
- Arm/Arch.c
- Arm/Helper.asm | RVCT
- Arm/Helper.S | GCC
- Arm/SecEntryPoint.S | GCC
- Arm/SecEntryPoint.asm | RVCT
-
-[Sources.AARCH64]
- AArch64/Arch.c
- AArch64/Helper.S
- AArch64/SecEntryPoint.S
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
- ArmCpuLib
- ArmLib
- ArmPlatformLib
- ArmPlatformSecLib
- ArmTrustedMonitorLib
- BaseLib
- DebugLib
- DebugAgentLib
- IoLib
- ArmGicLib
- PrintLib
- SerialPortLib
-
-[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
-
-[FixedPcd.common]
-
- gArmTokenSpaceGuid.PcdTrustzoneSupport
- gArmTokenSpaceGuid.PcdVFPEnabled
-
- gArmTokenSpaceGuid.PcdArmScr
- gArmTokenSpaceGuid.PcdArmNonSecModeTransition
-
- gArmTokenSpaceGuid.PcdSecureFvBaseAddress
- gArmTokenSpaceGuid.PcdSecureFvSize
-
- gArmTokenSpaceGuid.PcdFvBaseAddress
-
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
-
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-
-[FixedPcd.ARM]
- gArmTokenSpaceGuid.PcdArmNsacr
diff --git a/ArmPlatformPkg/Sec/SecInternal.h b/ArmPlatformPkg/Sec/SecInternal.h deleted file mode 100644 index 111123725b..0000000000 --- a/ArmPlatformPkg/Sec/SecInternal.h +++ /dev/null @@ -1,83 +0,0 @@ -/** @file
-* Main file supporting the SEC Phase on ARM PLatforms
-*
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef __SEC_H__
-#define __SEC_H__
-
-#include <Base.h>
-#include <Library/ArmLib.h>
-#include <Library/ArmCpuLib.h>
-#include <Library/ArmPlatformLib.h>
-#include <Library/ArmPlatformSecLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
-
-VOID
-TrustedWorldInitialization (
- IN UINTN MpId,
- IN UINTN SecBootMode
- );
-
-VOID
-NonTrustedWorldTransition (
- IN UINTN MpId,
- IN UINTN JumpAddress
- );
-
-VOID
-ArmSetupGicNonSecure (
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
-);
-
-VOID
-enter_monitor_mode (
- IN UINTN MonitorEntryPoint,
- IN UINTN MpId,
- IN UINTN SecBootMode,
- IN VOID* MonitorStackBase
- );
-
-VOID
-return_from_exception (
- IN UINTN NonSecureBase
- );
-
-VOID
-copy_cpsr_into_spsr (
- VOID
- );
-
-VOID
-set_non_secure_mode (
- IN ARM_PROCESSOR_MODE Mode
- );
-
-VOID
-SecCommonExceptionEntry (
- IN UINT32 Entry,
- IN UINTN LR
- );
-
-VOID
-EFIAPI
-ArmSecArchTrustzoneInit (
- VOID
- );
-
-#endif
|