ArmPkg: Introduce ArmCpuLib to abstract ARM Cpu specific initialization

Every CPUs have their own initialization requirements.
This library allows to allows to abstract these initialization requirements
into the ARM Platform common components.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12448 6f19259b-4bc3-4df7-8a09-765794883524

11 files changed, 237 insertions, 274 deletions

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index bc5bb32f3b..c36773dd89 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -55,7 +55,6 @@
 [PcdsFixedAtBuild.common]

   # These PCDs should be FeaturePcds. But we used these PCDs as an '#if' in an ASM file.

   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.

-  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000003

   gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038

     

   # Stack for CPU Cores in Secure Mode

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
index 41022b983e..16aa124e93 100644
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
@@ -31,6 +31,7 @@
 

 [LibraryClasses.common]

   ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf

+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf

   ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf

   

   # ARM PL390 General Interrupt Driver in Secure and Non-secure

@@ -44,7 +45,7 @@
 [BuildOptions]

   RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

 

-  GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

+  GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a8 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

 

   XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

 

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
index 2169ed8c7f..b17d59e0ee 100644
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
@@ -31,6 +31,7 @@
 

 [LibraryClasses.common]

   ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf

+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf

   ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf

   

   # ARM PL390 General Interrupt Driver in Secure and Non-secure

@@ -44,7 +45,7 @@
 [BuildOptions]

   RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A9 --fpu=softvfp -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

 

-  GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

+  GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a9 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

 

   XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/ArmPlatformPkg/ArmRealViewEbPkg/Include/Platform

 

@@ -79,8 +80,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x43FE0000

   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000

 

-  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1

-  

   # Stacks for MPCores in Secure World

   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x4B000000

   # Stacks for MPCores in Monitor Mode

diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
index 2d30f188af..1324da2cd4 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
@@ -35,6 +35,7 @@
 
 [LibraryClasses.common]
   ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
   ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
   ArmTrustZoneLib|ArmPkg/Library/ArmTrustZoneLib/ArmTrustZoneLib.inf
 
@@ -174,7 +175,6 @@
   gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
   gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
   
-  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
   gArmTokenSpaceGuid.PcdVFPEnabled|1
   
   # Stacks for MPCores in Secure World
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc
index bd021d61df..5f456a2fc0 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc
@@ -31,6 +31,7 @@
 
 [LibraryClasses.common]
   ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
+  ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
   ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
   
   ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
@@ -89,7 +90,6 @@
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
 
-  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|1
   gArmTokenSpaceGuid.PcdVFPEnabled|1
   
   # Stacks for MPCores in Secure World
diff --git a/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt b/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
index 91f586ef76..e591767a10 100644
--- a/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
+++ b/ArmPlatformPkg/Documentation/ArmPlatformPkg.txt
@@ -31,7 +31,6 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize        : Size of the sta
 # CPU / Architectural controllers

 gArmTokenSpaceGuid.PcdGicDistributorBase        : Base address of the Distributor of your General Interrupt Controller

 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller

-gArmPlatformTokenSpaceGuid.PcdMPCoreSupport     : Set to 1 when MP Core platforms

 

 # Memory Regions

 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize  : Size of the region reserve for PI & UEFI

diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index 1da26356fc..5853dfba3e 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -14,13 +14,12 @@
 **/
 
 #include <Library/DebugAgentLib.h>
-#include <Library/PcdLib.h>
 #include <Library/PrintLib.h>
 #include <Library/BaseMemoryLib.h>
-#include <Library/ArmLib.h>
 #include <Library/SerialPortLib.h>
 #include <Library/ArmPlatformLib.h>
 #include <Library/ArmGicLib.h>
+#include <Library/ArmCpuLib.h>
 
 #include "SecInternal.h"
 
@@ -39,8 +38,10 @@ CEntryPoint (
 
   // Primary CPU clears out the SCU tag RAMs, secondaries wait
   if (IS_PRIMARY_CORE(MpId)) {
-    if (FixedPcdGet32(PcdMPCoreSupport)) {
-      ArmInvalidScu ();
+    ArmCpuSetup (MpId);
+
+    if (ArmIsMpCore()) {
+      ArmCpuSynchronizeSignal (ARM_CPU_EVENT_BOOT_MEM_INIT);
     }
 
     // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
@@ -58,6 +59,15 @@ CEntryPoint (
     // Now we've got UART, make the check:
     // - The Vector table must be 32-byte aligned
     ASSERT(((UINT32)SecVectorTable & ((1 << 5)-1)) == 0);
+
+    // Enable the GIC distributor and CPU Interface
+    // - no other Interrupts are enabled,  doesn't have to worry about the priority.
+    // - all the cores are in secure state, use secure SGI's
+    ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+  } else {
+    // Enable the GIC CPU Interface
+    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
   }
 
   // Invalidate the data cache. Doesn't have to do the Data cache clean.
@@ -72,13 +82,7 @@ CEntryPoint (
   // Enable Full Access to CoProcessors
   ArmWriteCPACR (CPACR_CP_FULL_ACCESS);
 
-  // Enable SWP instructions
-  ArmEnableSWPInstruction ();
-
-  // Enable program flow prediction, if supported.
-  ArmEnableBranchPrediction ();
-
-  if (FixedPcdGet32(PcdVFPEnabled)) {
+  if (FixedPcdGet32 (PcdVFPEnabled)) {
     ArmEnableVFP();
   }
 
@@ -89,7 +93,7 @@ CEntryPoint (
 
     // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.
     // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM
-    if (FeaturePcdGet(PcdSystemMemoryInitializeInSec)) {
+    if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
       // Initialize system memory (DRAM)
       ArmPlatformInitializeSystemMemory ();
     }
@@ -104,9 +108,9 @@ CEntryPoint (
     ASSERT(PcdGet32(PcdCPUCoresSecMonStackBase) != 0);
     ASSERT(PcdGet32(PcdCPUCoreSecMonStackSize) != 0);
 
-    if (FixedPcdGet32(PcdMPCoreSupport)) {
+    if (ArmIsMpCore()) {
       // Setup SMP in Non Secure world
-      ArmSetupSmpNonSecure (GET_CORE_ID(MpId));
+      ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
     }
 
     // Enter Monitor Mode
@@ -120,35 +124,18 @@ CEntryPoint (
     if (IS_PRIMARY_CORE(MpId)) {
       ArmPlatformTrustzoneInit ();
 
-      // Wake up the secondary cores by sending a interrupt to everyone else
-      // NOTE 1: The Software Generated Interrupts are always enabled on Cortex-A9
-      //         MPcore test chip on Versatile Express board, So the Software doesn't have to
-      //         enable SGI's explicitly.
-      //      2: As no other Interrupts are enabled,  doesn't have to worry about the priority.
-      //      3: As all the cores are in secure state, use secure SGI's
-      //
-
-      ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
-      ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
-
-      // Send SGI to all Secondary core to wake them up from WFI state.
-      ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+      // Waiting for the Primary Core to have finished to initialize the Secure World
+      ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);
     } else {
       // The secondary cores need to wait until the Trustzone chipsets configuration is done
       // before switching to Non Secure World
 
-      // Enabled GIC CPU Interface
-      ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
-
-      // Waiting for the SGI from the primary core
-      ArmCallWFI();
-
-      // Acknowledge the interrupt and send End of Interrupt signal.
-      ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
+      // Waiting for the Primary Core to have finished to initialize the Secure World
+      ArmCpuSynchronizeWait (ARM_CPU_EVENT_SECURE_INIT);
     }
 
     // Transfer the interrupt to Non-secure World
-    ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+    ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
 
     // Write to CP15 Non-secure Access Control Register :
     //   - Enable CP10 and CP11 accesses in NS World
@@ -165,12 +152,6 @@ CEntryPoint (
       SerialPrint ("Trust Zone Configuration is disabled\n\r");
     }
 
-    // Trustzone is not enabled, just enable the Distributor and CPU interface
-    if (IS_PRIMARY_CORE(MpId)) {
-      ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
-    }
-    ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
-
     // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
     // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
     // Status Register as the the current one (CPSR).
diff --git a/ArmPlatformPkg/Sec/Sec.inf b/ArmPlatformPkg/Sec/Sec.inf
index 343a7ac4fd..5079f29da5 100644
--- a/ArmPlatformPkg/Sec/Sec.inf
+++ b/ArmPlatformPkg/Sec/Sec.inf
@@ -1,70 +1,70 @@
-#/** @file
-#  SEC - Reset vector code that jumps to C and loads DXE core
-#  
-#  Copyright (c) 2011, ARM Limited. All rights reserved.
-#  
-#  This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http://opensource.org/licenses/bsd-license.php                                            
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-#  
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = ArmPlatformSec
-  FILE_GUID                      = c536bbfe-c813-4e48-9f90-01fe1ecf9d54
-  MODULE_TYPE                    = SEC
-  VERSION_STRING                 = 1.0
-
-[Sources.ARM]
-  Helper.asm           | RVCT
-  Helper.S             | GCC
-  Sec.c
-  SecEntryPoint.S      | GCC
-  SecEntryPoint.asm    | RVCT
-  Exception.asm        | RVCT
-  Exception.S          | GCC
-  
-[Packages]
-  MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
-  ArmPkg/ArmPkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-
-[LibraryClasses]
-  ArmLib
-  ArmPlatformLib
-  BaseLib
-  DebugLib
-  DebugAgentLib
-  IoLib
-  ArmGicSecLib
-  PrintLib
-  SerialPortLib
-  
-[FeaturePcd]
-  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
-  
-[FixedPcd]
-  gArmTokenSpaceGuid.PcdVFPEnabled
-  gArmPlatformTokenSpaceGuid.PcdMPCoreSupport
-  
-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
-  gArmTokenSpaceGuid.PcdArmPrimaryCore
-  
-  gArmTokenSpaceGuid.PcdFvBaseAddress
-  
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
-  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
-  
-  gArmTokenSpaceGuid.PcdGicDistributorBase
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-  
-  gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize  
+#/** @file

+#  SEC - Reset vector code that jumps to C and loads DXE core

+#  

+#  Copyright (c) 2011, ARM Limited. All rights reserved.

+#  

+#  This program and the accompanying materials                          

+#  are licensed and made available under the terms and conditions of the BSD License         

+#  which accompanies this distribution.  The full text of the license may be found at        

+#  http://opensource.org/licenses/bsd-license.php                                            

+#

+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+#  

+#**/

+

+[Defines]

+  INF_VERSION                    = 0x00010005

+  BASE_NAME                      = ArmPlatformSec

+  FILE_GUID                      = c536bbfe-c813-4e48-9f90-01fe1ecf9d54

+  MODULE_TYPE                    = SEC

+  VERSION_STRING                 = 1.0

+

+[Sources.ARM]

+  Helper.asm           | RVCT

+  Helper.S             | GCC

+  Sec.c

+  SecEntryPoint.S      | GCC

+  SecEntryPoint.asm    | RVCT

+  Exception.asm        | RVCT

+  Exception.S          | GCC

+  

+[Packages]

+  MdePkg/MdePkg.dec

+  MdeModulePkg/MdeModulePkg.dec

+  ArmPkg/ArmPkg.dec

+  ArmPlatformPkg/ArmPlatformPkg.dec

+

+[LibraryClasses]

+  ArmCpuLib

+  ArmLib

+  ArmPlatformLib

+  BaseLib

+  DebugLib

+  DebugAgentLib

+  IoLib

+  ArmGicSecLib

+  PrintLib

+  SerialPortLib

+  

+[FeaturePcd]

+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec

+  

+[FixedPcd]

+  gArmTokenSpaceGuid.PcdVFPEnabled

+  

+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask

+  gArmTokenSpaceGuid.PcdArmPrimaryCore

+  

+  gArmTokenSpaceGuid.PcdFvBaseAddress

+  

+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase

+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize

+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize

+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase

+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize

+  

+  gArmTokenSpaceGuid.PcdGicDistributorBase

+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

+  

+  gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize  

diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.S b/ArmPlatformPkg/Sec/SecEntryPoint.S
index 7f13057f6b..f92a2dffba 100644
--- a/ArmPlatformPkg/Sec/SecEntryPoint.S
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.S
@@ -13,15 +13,11 @@
 

 #include <AutoGen.h>

 #include <AsmMacroIoLib.h>

-#include <Base.h>

-#include <Library/PcdLib.h>

-#include <Library/ArmPlatformLib.h>

+#include "SecInternal.h"

 

 .text

 .align 3

 

-GCC_ASM_EXPORT(_ModuleEntryPoint)

-

 GCC_ASM_IMPORT(CEntryPoint)

 GCC_ASM_IMPORT(ArmPlatformSecBootAction)

 GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)

@@ -30,13 +26,10 @@ GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
 GCC_ASM_IMPORT(ArmWriteVBar)

 GCC_ASM_IMPORT(ArmReadMpidr)

 GCC_ASM_IMPORT(SecVectorTable)

-

-#if (FixedPcdGet32(PcdMPCoreSupport))

-GCC_ASM_IMPORT(ArmIsScuEnable)

-#endif

+GCC_ASM_IMPORT(ArmCpuSynchronizeWait)

+GCC_ASM_EXPORT(_ModuleEntryPoint)

 

 StartupAddr:        .word       ASM_PFX(CEntryPoint)

-SecVectorTableAddr: .word	ASM_PFX(SecVectorTable)

 

 ASM_PFX(_ModuleEntryPoint):

   // First ensure all interrupts are disabled

@@ -65,14 +58,11 @@ _IdentifyCpu:
   // Only the primary core initialize the memory (SMC)

   beq   _InitMem

   

-#if (FixedPcdGet32(PcdMPCoreSupport))

-  // ... The secondary cores wait for SCU to be enabled

-_WaitForEnabledScu:

-  bl    ASM_PFX(ArmIsScuEnable)

-  tst   r1, #1

-  beq   _WaitForEnabledScu

+_WaitInitMem:

+  mov   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT

+  bl    ASM_PFX(ArmCpuSynchronizeWait)

+  // Now the Init Mem is initialized, we setup the secondary core stacks

   b     _SetupSecondaryCoreStack

-#endif

   

 _InitMem:

   // Initialize Init Boot Memory

@@ -110,7 +100,7 @@ _SetupSecondaryCoreStack:
 

   // Get the base of the stack for the secondary cores

   LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)

-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)

   add   r1, r1, r2

 

   // StackOffset = CorePos * StackSize

diff --git a/ArmPlatformPkg/Sec/SecEntryPoint.asm b/ArmPlatformPkg/Sec/SecEntryPoint.asm
index c39b80a85f..e4ceb697f8 100644
--- a/ArmPlatformPkg/Sec/SecEntryPoint.asm
+++ b/ArmPlatformPkg/Sec/SecEntryPoint.asm
@@ -1,134 +1,126 @@
-//
-//  Copyright (c) 2011, ARM Limited. All rights reserved.
-//  
-//  This program and the accompanying materials                          
-//  are licensed and made available under the terms and conditions of the BSD License         
-//  which accompanies this distribution.  The full text of the license may be found at        
-//  http://opensource.org/licenses/bsd-license.php                                            
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-//
-//
-
-#include <AutoGen.h>
-#include <AsmMacroIoLib.h>
-#include <Base.h>
-#include <Library/PcdLib.h>
-#include <Library/ArmPlatformLib.h>
-
-  INCLUDE AsmMacroIoLib.inc
-  
-  IMPORT  CEntryPoint
-  IMPORT  ArmPlatformSecBootAction
-  IMPORT  ArmPlatformInitializeBootMemory
-  IMPORT  ArmDisableInterrupts
-  IMPORT  ArmDisableCachesAndMmu
-  IMPORT  ArmWriteVBar
-  IMPORT  ArmReadMpidr
-  IMPORT  SecVectorTable
-  EXPORT  _ModuleEntryPoint
-
-#if (FixedPcdGet32(PcdMPCoreSupport))
-  IMPORT  ArmIsScuEnable
-#endif
-  
-  PRESERVE8
-  AREA    SecEntryPoint, CODE, READONLY
-  
-StartupAddr        DCD      CEntryPoint
-
-_ModuleEntryPoint
-  // First ensure all interrupts are disabled
-  blx   ArmDisableInterrupts
-
-  // Ensure that the MMU and caches are off
-  blx   ArmDisableCachesAndMmu
-
-  // Jump to Platform Specific Boot Action function
-  blx   ArmPlatformSecBootAction
-
-  // Set VBAR to the start of the exception vectors in Secure Mode
-  ldr   r0, =SecVectorTable
-  blx   ArmWriteVBar
-
-_IdentifyCpu 
-  // Identify CPU ID
-  bl    ArmReadMpidr
-  // Get ID of this CPU in Multicore system
-  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
-  and   r5, r0, r1
-  
-  // Is it the Primary Core ?
-  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)
-  cmp   r5, r1
-  // Only the primary core initialize the memory (SMC)
-  beq   _InitMem
-  
-#if (FixedPcdGet32(PcdMPCoreSupport))
-  // ... The secondary cores wait for SCU to be enabled
-_WaitForEnabledScu
-  bl    ArmIsScuEnable
-  tst   r1, #1
-  beq   _WaitForEnabledScu
-  b     _SetupSecondaryCoreStack
-#endif
-  
-_InitMem
-  // Initialize Init Boot Memory
-  bl    ArmPlatformInitializeBootMemory
-  
-  // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
-  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
-
-_SetupPrimaryCoreStack
-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)
-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)
-  // Calculate the Top of the Stack
-  add   r2, r2, r3
-  LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)
-
-  // The reserved space for global variable must be 8-bytes aligned for pushing
-  // 64-bit variable on the stack
-  SetPrimaryStack (r2, r3, r1)
-
-  // Set all the SEC global variables to 0
-  mov     r3, sp
-  mov     r1, #0x0
-_InitGlobals
-  str     r1, [r3], #4
-  cmp     r3, r2
-  blt     _InitGlobals
-
-  b     _PrepareArguments
-
-_SetupSecondaryCoreStack
-  // Get the Core Position (ClusterId * 4) + CoreId
-  GetCorePositionInStack(r0, r5, r1)
-  // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
-  add   r0, r0, #1
-
-  // Get the base of the stack for the secondary cores
-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
-  add   r1, r1, r2
-
-  // StackOffset = CorePos * StackSize
-  mul   r0, r0, r2
-  // SP = StackBase + StackOffset
-  add   sp, r1, r0
-
-
-_PrepareArguments
-  // Move sec startup address into a data register
-  // Ensure we're jumping to FV version of the code (not boot remapped alias)
-  ldr   r3, StartupAddr
-  
-  // Jump to SEC C code
-  //    r0 = mp_id
-  mov   r0, r5
-  blx   r3
-  
-_NeverReturn
-  b _NeverReturn
-  END
+//

+//  Copyright (c) 2011, ARM Limited. All rights reserved.

+//  

+//  This program and the accompanying materials                          

+//  are licensed and made available under the terms and conditions of the BSD License         

+//  which accompanies this distribution.  The full text of the license may be found at        

+//  http://opensource.org/licenses/bsd-license.php                                            

+//

+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+//

+//

+

+#include <AutoGen.h>

+#include <AsmMacroIoLib.h>

+#include "SecInternal.h"

+

+  INCLUDE AsmMacroIoLib.inc

+  

+  IMPORT  CEntryPoint

+  IMPORT  ArmPlatformSecBootAction

+  IMPORT  ArmPlatformInitializeBootMemory

+  IMPORT  ArmDisableInterrupts

+  IMPORT  ArmDisableCachesAndMmu

+  IMPORT  ArmWriteVBar

+  IMPORT  ArmReadMpidr

+  IMPORT  SecVectorTable

+  IMPORT  ArmCpuSynchronizeWait

+  EXPORT  _ModuleEntryPoint

+

+  PRESERVE8

+  AREA    SecEntryPoint, CODE, READONLY

+  

+StartupAddr        DCD      CEntryPoint

+

+_ModuleEntryPoint

+  // First ensure all interrupts are disabled

+  blx   ArmDisableInterrupts

+

+  // Ensure that the MMU and caches are off

+  blx   ArmDisableCachesAndMmu

+

+  // Jump to Platform Specific Boot Action function

+  blx   ArmPlatformSecBootAction

+

+  // Set VBAR to the start of the exception vectors in Secure Mode

+  ldr   r0, =SecVectorTable

+  blx   ArmWriteVBar

+

+_IdentifyCpu 

+  // Identify CPU ID

+  bl    ArmReadMpidr

+  // Get ID of this CPU in Multicore system

+  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)

+  and   r5, r0, r1

+  

+  // Is it the Primary Core ?

+  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)

+  cmp   r5, r1

+  // Only the primary core initialize the memory (SMC)

+  beq   _InitMem

+  

+_WaitInitMem

+  mov   r0, #ARM_CPU_EVENT_BOOT_MEM_INIT

+  bl    ArmCpuSynchronizeWait

+  // Now the Init Mem is initialized, we setup the secondary core stacks

+  b     _SetupSecondaryCoreStack

+  

+_InitMem

+  // Initialize Init Boot Memory

+  bl    ArmPlatformInitializeBootMemory

+  

+  // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)

+  LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)

+

+_SetupPrimaryCoreStack

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)

+  // Calculate the Top of the Stack

+  add   r2, r2, r3

+  LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)

+

+  // The reserved space for global variable must be 8-bytes aligned for pushing

+  // 64-bit variable on the stack

+  SetPrimaryStack (r2, r3, r1)

+

+  // Set all the SEC global variables to 0

+  mov     r3, sp

+  mov     r1, #0x0

+_InitGlobals

+  str     r1, [r3], #4

+  cmp     r3, r2

+  blt     _InitGlobals

+

+  b     _PrepareArguments

+

+_SetupSecondaryCoreStack

+  // Get the Core Position (ClusterId * 4) + CoreId

+  GetCorePositionInStack(r0, r5, r1)

+  // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack

+  add   r0, r0, #1

+

+  // Get the base of the stack for the secondary cores

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)

+  add   r1, r1, r2

+

+  // StackOffset = CorePos * StackSize

+  mul   r0, r0, r2

+  // SP = StackBase + StackOffset

+  add   sp, r1, r0

+

+

+_PrepareArguments

+  // Move sec startup address into a data register

+  // Ensure we're jumping to FV version of the code (not boot remapped alias)

+  ldr   r3, StartupAddr

+  

+  // Jump to SEC C code

+  //    r0 = mp_id

+  mov   r0, r5

+  blx   r3

+  

+_NeverReturn

+  b _NeverReturn

+  END

diff --git a/ArmPlatformPkg/Sec/SecInternal.h b/ArmPlatformPkg/Sec/SecInternal.h
index a4685c1448..4d1b0f6089 100644
--- a/ArmPlatformPkg/Sec/SecInternal.h
+++ b/ArmPlatformPkg/Sec/SecInternal.h
@@ -17,10 +17,12 @@
 #define __SEC_H__

 

 #include <Base.h>

+#include <Library/ArmLib.h>

+#include <Library/ArmCpuLib.h>

+#include <Library/ArmPlatformLib.h>

 #include <Library/BaseLib.h>

 #include <Library/DebugLib.h>

-

-#include <Chipset/ArmV7.h>

+#include <Library/PcdLib.h>

 

 #define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)