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| author | Jeremy Linton <jeremy.linton@arm.com> | 2016-07-14 08:58:29 -0500 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2016-07-14 15:26:29 +0100 |
| commit | 162e789178c86c5ea4322bf639724822cc7db98d (patch) | |
| tree | 0417130f2ce1624f5b5706ed0eaaee568d0f25b1 /ArmPlatformPkg | |
| parent | e39d0569a67f2cac31ad79f8d16f059c27ed82e2 (diff) | |
| download | edk2-platforms-162e789178c86c5ea4322bf639724822cc7db98d.tar.xz | |
ArmPlatformPkg/ArmJuno: fix Juno PIO host bridge mapping
The Juno PIO mapping is 8M, so it should be using a 32-bit
PIO address translation. Further, PIO addresses should start
at 0 and be translated to/from the ARM MMIO region.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPlatformPkg')
| -rw-r--r-- | ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c index 06de6d5d9a..d549903309 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/XPressRich3.c @@ -72,7 +72,9 @@ HWPciRbInit ( PCI_TRACE ("PCIe Setting up Address Translation");
- PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64);
+ // The Juno PIO window is 8M, so we need full 32-bit PIO decoding.
+ PCIE_ROOTPORT_WRITE32 (PCIE_BAR_WIN, PCIE_BAR_WIN_SUPPORT_IO | PCIE_BAR_WIN_SUPPORT_IO32 |
+ PCIE_BAR_WIN_SUPPORT_MEM | PCIE_BAR_WIN_SUPPORT_MEM64);
// Setup the PCI Configuration Registers
// Offset 0a: SubClass 04 PCI-PCI Bridge
@@ -107,8 +109,9 @@ HWPciRbInit ( SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_ECAM_BASE, PCI_ECAM_BASE, PCI_ECAM_SIZE, PCI_ATR_TRSLID_PCIE_CONF);
TranslationTable += PCI_ATR_ENTRY_SIZE;
- // PCI IO Support
- SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, PCI_IO_BASE, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO);
+ // PCI IO Support, the PIO space is translated from the arm MMIO PCI_IO_BASE address to the PIO base address of 0
+ // AKA, PIO addresses used by endpoints are generally in the range of 0-64K.
+ SetTranslationAddressEntry (CpuIo, TranslationTable, PCI_IO_BASE, 0, PCI_IO_SIZE, PCI_ATR_TRSLID_PCIE_IO);
TranslationTable += PCI_ATR_ENTRY_SIZE;
// PCI MEM32 Support
|