ArmPlatformPkg/PrePeiCore: Reserve some memory on the top of the stack for Global Variables in XIP code

The size of this memory is controlled by a PCD. The Global Variable in this regsion are defined by their offset.

This memory region can be use to store the PEI Services Table Pointer.
Update the PeiServicesTablePointerLib to use this region instead of PcdPeiServicePtrAddr.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11803 6f19259b-4bc3-4df7-8a09-765794883524

10 files changed, 56 insertions, 28 deletions

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 7a9223bc6c..e9af5cbdb8 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -46,8 +46,6 @@
   # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
   gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002
   
-  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
-  
   # Stack for CPU Cores in Secure Mode
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004
   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005
@@ -65,6 +63,15 @@
 
   # Size of the region reserved for fixed address allocations (Reserved 128MB by default)
   gArmPlatformTokenSpaceGuid.PcdSystemMemoryFixRegionSize|0x08000000|UINT32|0x00000014
+
+  # Size to reserve in the primary core stack for PEI Global Variables
+  #  = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
+  gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
+  # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
+  # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped. 
+  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x4|UINT32|0x00000017
+  gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x4|UINT32|0x00000018
+
   #
   # ARM Primecells
   #
diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
index 96d2e0344f..c63844c919 100644
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
@@ -348,7 +348,6 @@
   # Stack for CPU Cores in Non Secure Mode

   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000  # Top of SEC Stack for Normal World

   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000     # Size of SEC Stack for Normal World

-  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004        # Pei Services Ptr just above stack

 

   # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize

   gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000       # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase

diff --git a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
index 3df9c715be..3159493d86 100644
--- a/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
+++ b/ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
@@ -352,7 +352,6 @@
   # Stacks for MPCores in Normal World
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000	# Top of SEC Stack for Normal World
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000	# Stack for each of the 4 CPU cores
-  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004        # Pei Services Ptr just above stack
 
   # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
   gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000       # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
index 2fd6fbf8fa..6aef292a52 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
+++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
@@ -383,7 +383,6 @@
   # Stacks for MPCores in Normal World
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000	# Top of SEC Stack for Normal World
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x00020000	# Stack for each of the 4 CPU cores
-  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004        # pei services ptr just above stack. Overlapped with the stack of CoreId 1
 
 
   # System Memory (1GB) 
diff --git a/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c b/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
index 9f25f4699f..8a47e8d8a7 100644
--- a/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
+++ b/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
@@ -39,7 +39,7 @@ SetPeiServicesTablePointer (
   UINTN *PeiPtrLoc;

   ASSERT (PeiServicesTablePointer != NULL);

 

-  PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr);

+  PeiPtrLoc = (UINTN *)(UINTN)(PcdGet32 (PcdCPUCoresNonSecStackBase) + (PcdGet32 (PcdCPUCoresNonSecStackSize) / 2) - PcdGet32 (PcdPeiServicePtrGlobalOffset));

   *PeiPtrLoc = (UINTN)PeiServicesTablePointer;

 }

 

@@ -63,7 +63,7 @@ GetPeiServicesTablePointer (
 {

   UINTN *PeiPtrLoc;

 

-  PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr);

+  PeiPtrLoc = (UINTN *)(UINTN)(PcdGet32 (PcdCPUCoresNonSecStackBase) + (PcdGet32 (PcdCPUCoresNonSecStackSize) / 2) - PcdGet32 (PcdPeiServicePtrGlobalOffset));

   return (CONST EFI_PEI_SERVICES **)*PeiPtrLoc;

 }

 

diff --git a/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf b/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
index f9860b63b7..33f2457b7e 100644
--- a/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+++ b/ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
@@ -40,4 +40,7 @@
   DebugLib

   

 [Pcd]

-  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr

+  gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset

+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase

+  gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize

+  

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
index 53c16ccb6f..ffa4a46da9 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
@@ -1,22 +1,21 @@
 //
 //  Copyright (c) 2011, ARM Limited. All rights reserved.
 //  
-# This program and the accompanying materials                          
-#  are licensed and made available under the terms and conditions of the BSD License         
-#  which accompanies this distribution.  The full text of the license may be found at        
-#  http:#opensource.org/licenses/bsd-license.php                                            
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-#
-#
+//  This program and the accompanying materials                          
+//  are licensed and made available under the terms and conditions of the BSD License         
+//  which accompanies this distribution.  The full text of the license may be found at        
+//  http://opensource.org/licenses/bsd-license.php                                            
+//
+//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+//
+//
 
 #include <AsmMacroIoLib.h>
 #include <Base.h>
 #include <Library/PcdLib.h>
 #include <AutoGen.h>
 
-#start of the code section
 .text
 .align 3
 
@@ -45,9 +44,17 @@ _SetupStack:
   add     r3,r3,r2,LSR #1   @ r3 = stack_offset + (stack_size/2)   <-- the top half is for the heap
   mov     sp, r3
 
-  # lr points to area in reset vector block containing PEI core address. lr needs to
-  # be saved from the beginning as the _ModuleEntryPoint could call helper functions
-  # that will overwrite 'lr'
+  # Only allocate memory in top of the primary core stack
+  cmp   r0, #0
+  bne   _PrepareArguments
+
+_AllocateGlobalPeiVariables:
+  # Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
+  LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
+  sub   sp, sp, r1
+
+_PrepareArguments:
+  # The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
   LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
   add   r2, r2, #4
   ldr   r1, [r2]
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
index de5fac15f8..231c14e36b 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
@@ -33,15 +33,25 @@ _ModuleEntryPoint
 

 _SetupStack

   // Setup Stack for the 4 CPU cores

-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)

-  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)

+  LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)

   

-  mov     r3,r0         // r3 = core_id

-  mul     r3,r3,r2      // r3 = core_id * stack_size = offset from the stack base

-  add     r3,r3,r1      // r3 = stack_base + offset

-  add     r3,r3,r2,LSR #1   // r3 = stack_offset + (stack_size/2)   <-- the top half is for the heap

-  mov     sp, r3

+  mov   r3, r0              // r3 = core_id

+  mul   r3, r3, r2          // r3 = core_id * stack_size = offset from the stack base

+  add   r3, r3, r1          // r3 = stack_base + offset

+  add   r3, r3, r2, LSR #1  // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap

+  mov   sp, r3

 

+  // Only allocate memory in top of the primary core stack

+  cmp   r0, #0

+  bne   _PrepareArguments

+

+_AllocateGlobalPeiVariables

+  // Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)

+  LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)

+  sub   sp, sp, r1

+

+_PrepareArguments

   // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector

   LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)

   add   r2, r2, #4

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
index 385b407363..4ca81f5a40 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -59,5 +59,7 @@
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase

   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize

   

+  gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize

+  

   gArmTokenSpaceGuid.PcdGicDistributorBase

   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
index 58b8e339ed..c14e7353c6 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
@@ -57,5 +57,7 @@
   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase

   gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize

   

+  gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize

+  

   gArmTokenSpaceGuid.PcdGicDistributorBase

   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase