diff options
| author | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-02-15 20:40:51 +0000 |
|---|---|---|
| committer | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-02-15 20:40:51 +0000 |
| commit | 026e30c4bb80a73ac7c5c286711ae07b1c51108b (patch) | |
| tree | 84fbc585ed86e924d54382baebef00ac7870e891 /BeagleBoardPkg/Sec/Clock.c | |
| parent | 95572bd1b8b55fff0b714b3e3a5f923f38eae460 (diff) | |
| download | edk2-platforms-026e30c4bb80a73ac7c5c286711ae07b1c51108b.tar.xz | |
Cleanup SerailIO drivers to have a device path and use PCD settings for various stuff. Also clean up a few coding convention items.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10009 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BeagleBoardPkg/Sec/Clock.c')
| -rw-r--r-- | BeagleBoardPkg/Sec/Clock.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/BeagleBoardPkg/Sec/Clock.c b/BeagleBoardPkg/Sec/Clock.c index 2d814e49e9..8b05938bcb 100644 --- a/BeagleBoardPkg/Sec/Clock.c +++ b/BeagleBoardPkg/Sec/Clock.c @@ -25,9 +25,9 @@ ClockInit ( //DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
// Enable PLL5 and set to 120 MHz as a reference clock.
- MmioWrite32(CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
- MmioWrite32(CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
- MmioWrite32(CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
+ MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
+ MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
+ MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
// Turn on functional & interface clocks to the USBHOST power domain
MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE
|