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| author | Olivier Martin <olivier.martin@arm.com> | 2014-01-10 11:27:31 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-01-10 11:27:31 +0000 |
| commit | c357fd6a1f79e2d7b0a1bd01994b8d33925bfff5 (patch) | |
| tree | b65ae48d420d19197ab04b50acff06cadbde24e8 /BeagleBoardPkg | |
| parent | 18b24f924f06f2345c0410d145d14e1a9a500dc8 (diff) | |
| download | edk2-platforms-c357fd6a1f79e2d7b0a1bd01994b8d33925bfff5.tar.xz | |
ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64
The System Memory region might be out of the 32-bit memory space.
This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:
- # System Memory (2GB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
EFI Shell and Linux kernel boot successfully.
Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BeagleBoardPkg')
| -rwxr-xr-x | BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c b/BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c index 5524ddbcad..210e850c8d 100755 --- a/BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +++ b/BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c @@ -55,9 +55,9 @@ ArmPlatformGetVirtualMemoryMap ( }
// ReMap (Either NOR Flash or DRAM)
- VirtualMemoryTable[Index].PhysicalBase = PcdGet32(PcdSystemMemoryBase);
- VirtualMemoryTable[Index].VirtualBase = PcdGet32(PcdSystemMemoryBase);
- VirtualMemoryTable[Index].Length = PcdGet32(PcdSystemMemorySize);
+ VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[Index].Attributes = CacheAttributes;
// SOC Registers. L3 interconnects
|